发明申请
US20050213696A1 Clock data recovery circuit 失效
时钟数据恢复电路

Clock data recovery circuit
摘要:
A frequency divider generates frequency-divided input data by dividing a frequency of input data. A phase comparator detects a phase difference between a phase of a clock generated by a voltage control oscillator and a phase of the frequency-divided input data, and generates a phase difference signal to be used to eliminate the detected phase difference. The voltage control oscillator generates the clock by adjusting an oscillation frequency based on the phase difference signal. A data identifier identifies the input data using the clock generated by the voltage control oscillator.
公开/授权文献
信息查询
0/0