发明申请
- 专利标题: Clock data recovery circuit
- 专利标题(中): 时钟数据恢复电路
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申请号: US10517493申请日: 2003-05-01
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公开(公告)号: US20050213696A1公开(公告)日: 2005-09-29
- 发明人: Hirofumi Totsuka , Hitoyuki Tagami
- 申请人: Hirofumi Totsuka , Hitoyuki Tagami
- 国际申请: PCT/JP03/05584 WO 20030501
- 主分类号: H03L7/07
- IPC分类号: H03L7/07 ; H03L7/08 ; H04L7/033 ; H03D3/24
摘要:
A frequency divider generates frequency-divided input data by dividing a frequency of input data. A phase comparator detects a phase difference between a phase of a clock generated by a voltage control oscillator and a phase of the frequency-divided input data, and generates a phase difference signal to be used to eliminate the detected phase difference. The voltage control oscillator generates the clock by adjusting an oscillation frequency based on the phase difference signal. A data identifier identifies the input data using the clock generated by the voltage control oscillator.
公开/授权文献
- US07489757B2 Clock data recovery circuit 公开/授权日:2009-02-10