A strained channel transistor and method for forming the the strained channel transistor including a semiconductor rate; a gate dielectric overlying a channel region; a gate rode overlying the gate dielectric; source drain extension regions and source and drain (S/D) regions; wherein a sed dielectric portion selected from the group consisting of r of stressed offset spacers disposed adjacent the gate rode and a stressed dielectric layer disposed over the gate rode including the S/D regions is disposed to exert a strain channel region.