Invention Application
- Patent Title: Semiconductor integrated circuit with noise reduction circuit
- Patent Title (中): 具有降噪电路的半导体集成电路
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Application No.: US11012145Application Date: 2004-12-16
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Publication No.: US20050249005A1Publication Date: 2005-11-10
- Inventor: Hiroyuki Nakamoto , Kunihiko Gotoh
- Applicant: Hiroyuki Nakamoto , Kunihiko Gotoh
- Assignee: FUJITSU LIMITED
- Current Assignee: FUJITSU LIMITED
- Priority: JP2004-138953 20040507
- Main IPC: H01L27/04
- IPC: H01L27/04 ; G11C7/02 ; H01L21/822 ; H01L21/8234 ; H01L27/08 ; H01L27/088 ; H03F1/26 ; H03K19/003 ; H03K19/094
Abstract:
A semiconductor integrated circuit includes a substrate, a digital circuit formed on a triple well formed in the substrate, a first node configured to supply a well potential of the digital circuit, a second node separate from the first node, and a substrate-potential supplying circuit, formed on the substrate, having an input node to receive an input potential from the second node and an output node to supply a substrate potential to the substrate, the substrate-potential supplying circuit having no direct-current path into which a direct current substantially flows through the input node, and configured to generate at the output node an output potential following the input potential.
Public/Granted literature
- US07068548B2 Semiconductor integrated circuit with noise reduction circuit Public/Granted day:2006-06-27
Information query
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