发明申请
US20050262329A1 Processor architecture for executing two different fixed-length instruction sets
审中-公开
用于执行两个不同固定长度指令集的处理器架构
- 专利标题： Processor architecture for executing two different fixed-length instruction sets
- 专利标题（中）： 用于执行两个不同固定长度指令集的处理器架构
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申请号： US10644226申请日： 2003-08-19
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公开(公告)号： US20050262329A1公开(公告)日： 2005-11-24
- 发明人: Sivaram Krishnan , Mark Debbage , Sebastian Ziesler , Kanad Roy , Andrew Sturges , Prasenjit Biswas
- 申请人： Sivaram Krishnan , Mark Debbage , Sebastian Ziesler , Kanad Roy , Andrew Sturges , Prasenjit Biswas
- 申请人地址： JP Tokyo
- 专利权人： Hitachi, Ltd.
- 当前专利权人： Hitachi, Ltd.
- 当前专利权人地址： JP Tokyo
- 主分类号： G06F9/30
- IPC分类号： G06F9/30 ; G06F9/318 ; G06F9/32
摘要：
A processor element, structured to execute a 32-bit fixed length instruction set architecture, is backward compatible with a 16-bit fixed length instruction set architecture by translating each of the 16-bit instructions into a sequence of one or more 32-bit instructions. Switching between 16-bit instruction execution and 32-bit instruction execution is accomplished by branch instructions that employ a least significant bit position of the address of the target of the branch to identify whether the target instruction is a 16-bit instruction or a 32-bit instruction.
公开/授权文献
- US1608992A Clutch-pedal operator 公开/授权日：1926-11-30
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