发明申请
- 专利标题: Clock generator and its control method
- 专利标题(中): 时钟发生器及其控制方法
-
申请号: US10968005申请日: 2004-10-20
-
公开(公告)号: US20050275471A1公开(公告)日: 2005-12-15
- 发明人: Hiroyuki Matsunami
- 申请人: Hiroyuki Matsunami
- 专利权人: FUJITSU LIMITED
- 当前专利权人: FUJITSU LIMITED
- 优先权: JP2004-170867 20040609
- 主分类号: G06F1/04
- IPC分类号: G06F1/04 ; H03L7/00 ; H03L7/18 ; H04L7/033
摘要:
To present a clock generator capable of spreading the spectrum of oscillation frequency by simple control in a small additional circuit, and its control method. A phase locked loop circuit is provided from a frequency phase comparator 11, an output clock signal PO is outputted from a voltage control oscillator (VCO) 14 by way of a charge pump circuit (CP) 12 and a loop filter (LF) 13, and is returned to the frequency phase comparator 11 by way of a frequency divider (DIV) 15. Detecting the phase difference of reference clock signal R and divided clock signal D, and locking the oscillation frequency of the output clock signal PO to specified frequency, a modulation signal M is outputted from a modulation pulse generator 1 regardless of phase locked control of phase locked loop circuit, and is superposed on phase comparison signal P, and thereby the oscillation frequency of output clock signal PO is modulated. An output clock signal PO having a predetermined spectrum spread characteristic can be obtained.
公开/授权文献
- US07113047B2 Clock generator and its control method 公开/授权日:2006-09-26
信息查询