发明申请
- 专利标题： Internal power supply voltage generation circuit that can suppress reduction in internal power supply voltage in neighborhood of lower limit region of external power supply voltage
- 专利标题（中）： 内部电源电压发生电路，可以抑制外部电源电压下限附近的内部电源电压的降低
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申请号： US11210845申请日： 2005-08-25
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公开(公告)号： US20050280465A1公开(公告)日： 2005-12-22
- 发明人: Fukashi Morishita
- 申请人： Fukashi Morishita
- 申请人地址： JP Tokyo
- 专利权人： Renesas Technology Corp.
- 当前专利权人： Renesas Technology Corp.
- 当前专利权人地址： JP Tokyo
- 优先权： JP10-032749(P) 19980216
- 主分类号： H02J1/00
- IPC分类号： H02J1/00 ; G05F1/46 ; G05F3/24 ; G11C11/407 ; H05B37/02
摘要：
An internal power supply voltage generation circuit includes a main amplifier that supplies a current from an external power supply node to an internal power supply line in accordance with the difference between a reference voltage from a reference voltage generation circuit and an internal power supply voltage on the internal power supply line. The current supply amount by the main amplifier is adjusted by a level adjust circuit, according to the difference between the external power supply voltage and the reference voltage. The internal power supply voltage generation circuit can suppress reduction in the internal power supply voltage in the vicinity of the lower limit area of the differential power supply voltage.
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