An N− layer is formed on a semiconductor substrate, with a BOX layer interposed. In the N− layer, a trench isolation region is formed to surround the N− layer to be an element forming region. The trench isolation region is formed to reach the BOX layer, from the surface of the N− layer. Between trench isolation region and the N− layer, a P type diffusion region 10a is formed. The P type diffusion region is formed continuously without any interruption, to be in contact with the entire surface of an inner sidewall of the trench isolation region surrounding the element forming region. In the element forming region of the N− layer, a prescribed semiconductor element is formed. Thus, a semiconductor device is formed, in which electrical isolation is established reliably, without increasing the area occupied by the element forming region.