发明申请
- 专利标题: TOP-OXIDE-EARLY PROCESS AND ARRAY TOP OXIDE PLANARIZATION
- 专利标题(中): 前氧化物早期工艺和顶部氧化物平面排列
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申请号: US10710566申请日: 2004-07-21
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公开(公告)号: US20060019443A1公开(公告)日: 2006-01-26
- 发明人: Deok-kee Kim , Ramachandra Divakaruni , Hiroyuki Akatsu , George Worth , Jay Strane , Byeong Kim
- 申请人: Deok-kee Kim , Ramachandra Divakaruni , Hiroyuki Akatsu , George Worth , Jay Strane , Byeong Kim
- 申请人地址: US NY Armonk
- 专利权人: INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人: INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人地址: US NY Armonk
- 主分类号: H01L21/467
- IPC分类号: H01L21/467 ; H01L21/8242
摘要:
Manufacturing yield of integrated circuits having differentiated areas such as array and support areas of a memory is improved by reducing height/step height difference between structures in the respective differentiated areas and is particularly effective in conjunction with top-oxide-early (TOE) and top-oxide-late processes. A novel planarization technique avoids damage of active devices, isolation structures and the like due to scratching, chipping or dishing which is particularly effective to improve manufacturing yield using TON processes and also using TOE and TOL processes when average height/step height is substantially equalized. Alternative mask materials such as polysilicon may also be used to simplify and/or improve control of processes.
公开/授权文献
- US07601646B2 Top-oxide-early process and array top oxide planarization 公开/授权日:2009-10-13
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