公开(公告)号：US20050077562A1

公开(公告)日：2005-04-14

申请号：US10605590

申请日：2003-10-10

Applicant: Rama Divakaruni ,  Johnathan Faltermeier ,  Michael Maldei ,  Jay Strane

Inventor： Rama Divakaruni ,  Johnathan Faltermeier ,  Michael Maldei ,  Jay Strane

IPC: H01L21/60 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L21/76897 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897

Abstract: A method of forming bitlines for a memory cell array of an integrated circuit and conductive lines interconnecting transistors of an external region outside of the memory cell array is provided. The method includes patterning troughs in a dielectric region covering the memory cell array according to a first critical dimension mask. Bitline contacts to a substrate and bitlines are formed in the troughs. Thereafter, conductive lines are formed which consist essentially of at least one material selected from the group consisting of metals and conductive compounds of metals in horizontally oriented patterns patterned by a second critical dimension mask, wherein the conductive lines interconnect the bitlines to transistors of external circuitry outside of the memory cell array, the conductive lines being interconnected to the bitlines only at peripheral edges of the memory cell array.

Abstract translation: 提供一种形成集成电路的存储单元阵列的位线的方法和将存储单元阵列外部的外部区域的晶体管互连的导线。 该方法包括根据第一临界尺寸掩模在覆盖存储单元阵列的电介质区域中图形化槽。 在槽中形成与基板和位线的位线接触。 此后，形成导线，其基本上由选自金属的金属和由第二关键尺寸掩模图案化的水平定向图案中的金属导电化合物组成的组中的至少一种材料组成，其中导线将位线互连到外部电路的晶体管 在存储单元阵列外部，导线仅在存储单元阵列的外围边缘处互连到位线。

公开(公告)号：US07601646B2

公开(公告)日：2009-10-13

申请号：US10710566

申请日：2004-07-21

Applicant: Deok-kee Kim ,  Ramachandra Divakaruni ,  Hiroyuki Akatsu ,  George Worth ,  Jay Strane ,  Byeong Kim

Inventor： Deok-kee Kim ,  Ramachandra Divakaruni ,  Hiroyuki Akatsu ,  George Worth ,  Jay Strane ,  Byeong Kim

IPC: H01L21/3065 ,  H01L21/308 ,  H01L21/311

CPC classification number: H01L27/10894 ,  H01L21/31053 ,  H01L27/10841 ,  H01L27/10897

Abstract: Manufacturing yield of integrated circuits having differentiated areas such as array and support areas of a memory is improved by reducing height/step height difference between structures in the respective differentiated areas and is particularly effective in conjunction with top-oxide-early (TOE) and top-oxide-late processes. A novel planarization technique avoids damage of active devices, isolation structures and the like due to scratching, chipping or dishing which is particularly effective to improve manufacturing yield using TON processes and also using TOE and TOL processes when average height/step height is substantially equalized. Alternative mask materials such as polysilicon may also be used to simplify and/or improve control of processes.

Abstract translation: 通过减少各个差异化区域中的结构之间的高度/台阶高差，可以提高具有差异化区域（例如存储器的阵列和支撑区域）的集成电路的制造产量，并且与顶部氧化物早期（TOE）和顶部 氧化物晚期过程。 新颖的平面化技术避免了由于刮擦，碎裂或凹陷而导致的有源器件，隔离结构等的损坏，这对于使用TON工艺提高制造产量特别有效，并且当平均高度/台阶高度基本相等时也使用TOE和TOL工艺。 还可以使用诸如多晶硅的替代掩模材料来简化和/或改进工艺的控制。

公开(公告)号：US20060019443A1

公开(公告)日：2006-01-26

申请号：US10710566

申请日：2004-07-21

Applicant: Deok-kee Kim ,  Ramachandra Divakaruni ,  Hiroyuki Akatsu ,  George Worth ,  Jay Strane ,  Byeong Kim

Inventor： Deok-kee Kim ,  Ramachandra Divakaruni ,  Hiroyuki Akatsu ,  George Worth ,  Jay Strane ,  Byeong Kim

IPC: H01L21/467 ,  H01L21/8242

CPC classification number: H01L27/10894 ,  H01L21/31053 ,  H01L27/10841 ,  H01L27/10897

Abstract: Manufacturing yield of integrated circuits having differentiated areas such as array and support areas of a memory is improved by reducing height/step height difference between structures in the respective differentiated areas and is particularly effective in conjunction with top-oxide-early (TOE) and top-oxide-late processes. A novel planarization technique avoids damage of active devices, isolation structures and the like due to scratching, chipping or dishing which is particularly effective to improve manufacturing yield using TON processes and also using TOE and TOL processes when average height/step height is substantially equalized. Alternative mask materials such as polysilicon may also be used to simplify and/or improve control of processes.

Abstract translation: 通过减少各个差异化区域中的结构之间的高度/台阶高差，可以提高具有差异化区域（例如存储器的阵列和支撑区域）的集成电路的制造产量，并且与顶部氧化物早期（TOE）和顶部 氧化物晚期过程。 新颖的平面化技术避免了由于刮擦，碎裂或凹陷而导致的有源器件，隔离结构等的损坏，这对于使用TON工艺提高制造产量特别有效，并且当平均高度/台阶高度基本相等时也使用TOE和TOL工艺。 还可以使用诸如多晶硅的替代掩模材料来简化和/或改进工艺的控制。

公开(公告)号：US20050130383A1

公开(公告)日：2005-06-16

申请号：US10707388

申请日：2003-12-10

Applicant: Ramachandra Divakaruni ,  Jay Strane

Inventor： Ramachandra Divakaruni ,  Jay Strane

IPC: H01L21/02 ,  H01L21/20 ,  H01L27/08

CPC classification number: H01L28/24 ,  H01L27/0802

Abstract: A suicide resistor for inclusion in a BEOL layer, and a method of forming the same that provides few additional manufacturing steps. The method allows formation of a passive resistor during BEOL processing without high temperature anneals that would damage other BEOL wiring structures. In particular, the method includes forming a silicide over a polysilicon base in a trough, where the silicide provides the desired resistivity and has a silicidation temperature less than a damaging temperature of the plurality of BEOL layers.

Abstract translation: 用于包含在BEOL层中的自杀电阻器及其形成方法，其提供了少量附加的制造步骤。 该方法允许在BEOL处理期间形成无源电阻，而不会导致其它BEOL布线结构的高温退火。 特别地，该方法包括在槽中的多晶硅基底上形成硅化物，其中硅化物提供期望的电阻率并且具有小于多个BEOL层的破坏温度的硅化温度。

公开(公告)号：US20070254479A1

公开(公告)日：2007-11-01

申请号：US11415922

申请日：2006-05-01

Applicant: Sunfei Fang ,  Randolph Knarr ,  Mahadevaiyer Krishnan ,  Christian Lavoie ,  Renee Mo ,  Balasubramanian Pranatharthiharan ,  Jay Strane

Inventor： Sunfei Fang ,  Randolph Knarr ,  Mahadevaiyer Krishnan ,  Christian Lavoie ,  Renee Mo ,  Balasubramanian Pranatharthiharan ,  Jay Strane

IPC: H01L21/44 ,  H01L21/302

CPC classification number: H01L21/28518 ,  C23F1/28 ,  C23F1/30 ,  C23F1/44

Abstract: The present invention relates to a method for forming self-aligned metal silicide contacts over at least two silicon-containing semiconductor regions that are spaced apart from each other by an exposed dielectric region. Preferably, each of the self-aligned metal silicide contacts so formed comprises at least nickel silicide and platinum silicide with a substantially smooth surface, and the exposed dielectric region is essentially free of metal and metal silicide. More preferably, the method comprises the steps of nickel or nickel alloy deposition, low-temperature annealing, nickel etching, high-temperature annealing, and aqua regia etching.

Abstract translation: 本发明涉及一种用于在由暴露的电介质区彼此间隔开的至少两个含硅半导体区域上形成自对准金属硅化物接触的方法。 优选地，如此形成的每个自对准金属硅化物触点至少包括具有基本平滑表面的至少硅化镍和铂硅化物，并且暴露的电介质区域基本上不含金属和金属硅化物。 更优选地，该方法包括镍或镍合金沉积，低温退火，镍蚀刻，高温退火和王水腐蚀的步骤。

公开(公告)号：US20050191862A1

公开(公告)日：2005-09-01

申请号：US10708408

申请日：2004-03-01

Applicant: Jay Strane

Inventor： Jay Strane

IPC: H01L21/768 ,  H01L21/8242 ,  H01L23/522

CPC classification number: H01L23/5222 ,  H01L21/7682 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A dual layer of polymeric material is deposited with a base layer and top layer resist onto an integrated circuit structure with topography. The base layer planarizes the surface and fills in the native topography. The base layer decomposes almost completely when exposed to an oxidizing environment. The top layer contains a high composition of oxidizing elements and is photosensitive. (i.e., the layer can be patterned by exposing normal lithographic techniques.) The patterning allows the creation of escape paths for the decomposition products of the underlying base layer. This structure is decomposed in an oxidizing ambient (or plasma) leaving behind a thin carbon-containing membrane. This membrane layer blocks deposition of future layers, creating air gaps in the structure.

Abstract translation: 聚合物材料的双层沉积有基底层和顶层抗蚀剂到具有形貌的集成电路结构上。 基层平坦化表面并填充原生地形。 当暴露于氧化环境时，基层几乎完全分解。 顶层含有高组分的氧化元素并且是光敏的。 （即，可以通过暴露正常光刻技术来对该层进行图案化）。图案化允许为下层基层的分解产物创建逃生路径。 该结构在氧化环境（或等离子体）中分解，留下薄碳膜。 该膜层阻止未来层的沉积，在结构中产生气隙。

公开(公告)号：US20070249149A1

公开(公告)日：2007-10-25

申请号：US11379651

申请日：2006-04-21

Applicant: Sadanand Deshpande ,  Jay Strane ,  Michael Belyansky ,  Christian Lavoie

Inventor： Sadanand Deshpande ,  Jay Strane ,  Michael Belyansky ,  Christian Lavoie

IPC: H01L21/4763 ,  H01L21/44

CPC classification number: H01L21/28518 ,  H01L21/3221 ,  H01L21/76829 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

Abstract: The use of nickel, Ni, based alloys that enables higher contact module which, in turn, provides the device designers additional gains in transistor speeds is provided. Specifically, the use of Ni based alloys for silicide formation in 90 nm technologies and beyond enables higher temperature (greater than 450° C.) processing in the contact module for advanced devices. This capability of higher thermal budget in processing stress inducing films in the contact module helps enhance device performance beyond what is possible with conventional pure Ni based silicides. Another benefit of this application is the deposition temperature of the contact dielectric (e.g., pre-metal dielectric) can be increased to enable moisture free, denser, higher quality films.

Abstract translation: 提供使用能够实现更高接触模块的镍，镍基合金，这又提供了器件设计器在晶体管速度方面的额外增益。 具体来说，使用Ni基合金在90nm以上的技术中进行硅化物形成，可以实现高级器件接触模块的高温（大于450°C）的加工。 在接触模块中处理应力诱导膜时，这种具有较高热预算的能力有助于提高器件性能，超出传统纯Ni基硅化物的可能性。 该应用的另一个好处是可以增加接触电介质的沉积温度（例如，预金属电介质），以实现无水分，更致密，更高质量的膜。

公开(公告)号：US06870211B1

公开(公告)日：2005-03-22

申请号：US10605590

申请日：2003-10-10

Applicant: Rama Divakaruni ,  Johnathan E. Faltermeier ,  Michael Maldei ,  Jay Strane

Inventor： Rama Divakaruni ,  Johnathan E. Faltermeier ,  Michael Maldei ,  Jay Strane

IPC: H01L21/60 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L21/76897 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897

Abstract: A method of forming bitlines for a memory cell array of an integrated circuit and conductive lines interconnecting transistors of an external region outside of the memory cell array is provided. The method includes patterning troughs in a dielectric region covering the memory cell array according to a first critical dimension mask. Bitline contacts to a substrate and bitlines are formed in the troughs. Thereafter, conductive lines are formed which consist essentially of at least one material selected from the group consisting of metals and conductive compounds of metals in horizontally oriented patterns patterned by a second critical dimension mask, wherein the conductive lines interconnect the bitlines to transistors of external circuitry outside of the memory cell array, the conductive lines being interconnected to the bitlines only at peripheral edges of the memory cell array.

Abstract translation: 提供一种形成集成电路的存储单元阵列的位线的方法和将存储单元阵列外部的外部区域的晶体管互连的导线。 该方法包括根据第一临界尺寸掩模在覆盖存储单元阵列的电介质区域中图形化槽。 在槽中形成与基板和位线的位线接触。 此后，形成导线，其基本上由选自金属的金属和由第二关键尺寸掩模图案化的水平定向图案中的金属导电化合物组成的组中的至少一种材料组成，其中导线将位线互连到外部电路的晶体管 在存储单元阵列外部，导线仅在存储单元阵列的外围边缘处互连到位线。