发明申请
US20060026223A1 Apparatus and method for reducing the latency of sum-addressed shifters
有权
用于减少和寻址移位器的延迟的装置和方法
- 专利标题： Apparatus and method for reducing the latency of sum-addressed shifters
- 专利标题（中）： 用于减少和寻址移位器的延迟的装置和方法
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申请号： US10902475申请日： 2004-07-29
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公开(公告)号： US20060026223A1公开(公告)日： 2006-02-02
- 发明人: Sang Dhong , Christian Jacobi , Silvia Mueller , Hiroo Nishikawa , Hwa-Joon Oh
- 申请人： Sang Dhong , Christian Jacobi , Silvia Mueller , Hiroo Nishikawa , Hwa-Joon Oh
- 申请人地址： US NY Armonk
- 专利权人： International Business Machines Corporation
- 当前专利权人： International Business Machines Corporation
- 当前专利权人地址： US NY Armonk
- 主分类号： G06F7/00
- IPC分类号： G06F7/00
摘要：
The present invention provides for calculating a shift amount as a function of a plurality of numbers. At least one decoder and the at least one adder are coupled in parallel. A shifter is configured to compute a value in a plurality of shift stages, and wherein a bit group of the shift amount is employable to affect at least one of the plurality of shift stages, thereby decreasing processing time.
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