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公开(公告)号：US10656945B2
公开(公告)日：2020-05-19
申请号：US13524105
申请日：2012-06-15
申请人： Christian Jacobi , Chung-Lung Kevin Chum , Timothy J. Slegel , Gustav E. Sittmann, III , Cynthia Sittmann
IPC分类号： G06F9/34 , G06F12/123 , G06F9/30 , G06F12/0815 , G06F12/126 , G06F12/0862 , G06F9/38
摘要： Executing a Next Instruction Access Intent instruction by a computer. The processor obtains an access intent instruction indicating an access intent. The access intent is associated with an operand of a next sequential instruction. The access intent indicates usage of the operand by one or more instructions subsequent to the next sequential instruction. The computer executes the access intent instruction. The computer obtains the next sequential instruction. The computer executes the next sequential instruction, whose execution comprises, based on the access intent, adjusting one or more cache behaviors for the operand of the next sequential instruction.
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公开(公告)号：US09442737B2
公开(公告)日：2016-09-13
申请号：US13524833
申请日：2012-06-15
申请人： Khary J. Alexander , Brenton F. Belmar , Christian Jacobi , Randall W. Philley , Anthony Saporito , Timothy J. Slegel
发明人： Khary J. Alexander , Brenton F. Belmar , Christian Jacobi , Randall W. Philley , Anthony Saporito , Timothy J. Slegel
CPC分类号： G06F9/3861 , G06F9/3004 , G06F9/30087 , G06F9/38 , G06F9/3857 , G06F9/466 , G06F9/467 , G06F9/52 , G06F9/524
摘要： Processing of transactions within a computing environment is facilitated by taking actions to increase the chances of successfully executing a transaction. A counter is maintained that provides a count of how often a transaction has aborted. The counter increments the count each time the transaction is aborted, and it is reset to zero upon successful completion of the transaction or an interruption leading to no more re-executions of the transaction. If the count reaches a threshold value, then an interrupt is presented and transaction execution is unsuccessful. However, before the count reaches the threshold, a number of actions may be taken to increase the chances of successfully executing the transaction. These actions include actions to be performed within the processor executing the transaction, and/or actions to be performed against conflicting processors.
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公开(公告)号：US09367323B2
公开(公告)日：2016-06-14
申请号：US13524871
申请日：2012-06-15
CPC分类号： G06F9/3861 , G06F9/3004 , G06F9/30087 , G06F9/3842 , G06F9/3857 , G06F9/466
摘要： An operation is provided to signal a processor that action is to be taken to facilitate execution of a transaction that has aborted one or more times. The operation is specified within an instruction or is itself an instruction. The instruction is executed based on detecting an abort of the transactions, and includes a field indicating how many times the transaction has aborted. The processor uses this information to determine what action is to be taken.
摘要翻译： 提供了一种操作来向处理器发出信号，该操作将采取行动来促进已经中止一次或多次的事务的执行。 操作在指令中指定或本身是指令。 该指令是基于检测到事务中止而执行的，并且包括指示事务中止多少次的字段。 处理器使用这些信息来确定要采取的行动。
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公开(公告)号：US09317460B2
公开(公告)日：2016-04-19
申请号：US13524903
申请日：2012-06-15
CPC分类号： G06F13/24 , G06F9/466 , G06F11/3636
摘要： A transaction is initiated within a computing environment, and based on detecting a program event recording event, an interrupt is presented for the transaction. Subsequent to the interrupt, one or more controls are set to inhibit presentation of another interrupt based on detecting another PER event. Thereafter, the transaction is re-executed and PER events detected during execution of the transaction are ignored.
摘要翻译： 事务在计算环境内启动，并且基于检测到程序事件记录事件，为事务呈现中断。 在中断之后，一个或多个控制被设置为基于检测另一个PER事件来抑制另一中断的呈现。 此后，事务被重新执行，并且在执行事务期间检测到的PER事件被忽略。
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公开(公告)号：US09298631B2
公开(公告)日：2016-03-29
申请号：US13524386
申请日：2012-06-15
CPC分类号： G06F12/084 , G06F9/467 , G06F11/1474 , G06F12/0828
摘要： Embodiments relate to controlling observability of transactional and non-transactional stores. An aspect includes receiving one or more store instructions. The one or more store instructions are initiated within an active transaction and include store data. The active transaction effectively delays committing stores to memory until successful completion of the active transaction. The store data is stored in a local storage buffer causing alterations to the local storage buffer from a first state to a second state. A signal is received that the active transaction has terminated. If the active transaction has terminated abnormally then: the local storage buffer is reverted back to the first state if the store data was stored by a transactional store instruction, and is propagated to a shared cache if the store instruction is non-transactional.
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6.发明授权History and alignment based cracking for store multiple instructions for optimizing operand store compare penalties 有权用于存储用于优化操作数存储的多个指令的基于历史和对齐的破解比较处罚公开(公告)号：US09135005B2
公开(公告)日：2015-09-15
申请号：US12695687
申请日：2010-01-28
申请人： Khary J. Alexander , Fadi Busaba , Brian Curran , Bruce Giamei , Christian Jacobi , James R. Mitchell
发明人： Khary J. Alexander , Fadi Busaba , Brian Curran , Bruce Giamei , Christian Jacobi , James R. Mitchell
CPC分类号： G06F9/30043 , G06F9/3017 , G06F9/3824 , G06F9/3838
摘要： Store multiple instructions are managed based on previous execution history and their alignment. At least one store multiple instruction is detected. A flag is determined to be associated with the at least one store multiple instruction. The flag indicates that the at least one store multiple instruction has previously encountered an operand store compare hazard. The at least one store multiple instruction is organized into a set of unit of operations. The set of unit of operations is executed. The executing avoids the operand store compare hazard previously encountered by the at least one store multiple instruction.
摘要翻译： 存储多个指令是根据以前的执行历史及其对齐方式进行管理的。 检测到至少一个存储多重指令。 确定标志与至少一个存储多重指令相关联。 该标志指示至少一个存储多指令先前已经遇到操作数存储比较危险。 将至少一个存储多个指令组织成一组操作单元。 执行一组操作单元。 该执行避免了由至少一个存储多个指令先前遇到的操作数存储比较危险。
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公开(公告)号：US09104399B2
公开(公告)日：2015-08-11
申请号：US12645716
申请日：2009-12-23
申请人： Fadi Busaba , Brian Curran , Lee Eisen , Christian Jacobi , David A. Schroter , Eric Schwarz
发明人： Fadi Busaba , Brian Curran , Lee Eisen , Christian Jacobi , David A. Schroter , Eric Schwarz
CPC分类号： G06F9/3001 , G06F9/30043 , G06F9/3017 , G06F9/3836 , G06F9/3867
摘要： A system and method for issuing a processor instruction to multiple processing sections arranged in an out-of-order processing pipeline architecture. The multiple processing sections include a first execution unit with a pipeline length and a second execution unit operating upon data produced by the first execution unit. An instruction issue unit accepts a complex instruction that is cracked into respective micro-ops for the first execution unit and the second execution unit. The instruction issue unit issues the first micro-op to the first execution unit to produce intermediate data. The instruction issue unit then delays for a time period corresponding to the processing pipeline length of the first execution unit. After the delay, a second micro-op is issued to the second execution unit.
摘要翻译： 一种用于向处理流水线结构排列的多个处理部分发出处理器指令的系统和方法。 多个处理部分包括具有流水线长度的第一执行单元和对由第一执行单元产生的数据进行操作的第二执行单元。 指令发布单元接受对于第一执行单元和第二执行单元破解为相应微操作的复杂指令。 指令发布单元向第一执行单元发出第一微操作以产生中间数据。 然后，指令发布单元延迟与第一执行单元的处理流水线长度对应的时间段。 在延迟之后，向第二执行单元发出第二个微操作。
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公开(公告)号：US08850166B2
公开(公告)日：2014-09-30
申请号：US12708284
申请日：2010-02-18
CPC分类号： G06F9/30043 , G06F9/3004 , G06F9/30087 , G06F9/30163 , G06F9/30167 , G06F9/3834
摘要： A Load/Store Disjoint instruction, when executed by a CPU, accesses operands from two disjoint memory locations and sets condition code indicators to indicate whether or not the two operands appeared to be accessed atomically by means of block-concurrent interlocked fetch with no intervening stores to the operands from other CPUs. In a Load Pair Disjoint form of the instruction, the accesses are loads and the disjoint data is stored in general registers.
摘要翻译： 加载/存储不相交指令在由CPU执行时，从两个不相交的存储器位置访问操作数，并设置条件代码指示符，以指示两个操作数是否似乎以原子方式访问，通过块并发互锁获取，无中间存储 到其他CPU的操作数。 在负载对不相交形式的指令中，访问是加载，不相交的数据存储在通用寄存器中。
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公开(公告)号：US08806179B2
公开(公告)日：2014-08-12
申请号：US12638314
申请日：2009-12-15
CPC分类号： G06F9/00 , G06F9/30 , G06F9/30003 , G06F9/3004 , G06F9/3009 , G06F9/30167 , G06F9/30181 , G06F9/3834 , G06F9/44 , G06F9/4418 , G06F9/45533 , G06F12/1475
摘要： A non-quiescing key setting facility is provided that enables manipulation of storage keys to be performed without quiescing operations of other processors of a multiprocessor system. With this facility, a storage key, which is accessible by a plurality of processors of the multiprocessor system, is updated absent a quiesce of operations of the plurality of processors. Since the storage key is updated absent quiescing of other operations, the storage key may be observed by a processor as having one value at the start of an operation performed by the processor and a second value at the end of the operation. A mechanism is provided to enable the operation to continue, avoiding a fatal exception.
摘要翻译： 提供了一种非静音密钥设置设备，其能够执行存储密钥的操作而不停止多处理器系统的其他处理器的操作。 利用这种设施，不需要多个处理器的操作的静止，更新可由多处理器系统的多个处理器访问的存储密钥。 由于存储密钥在没有其他操作的停顿的情况下更新，所以存储密钥可以被处理器观察到在处理器执行的操作开始时具有一个值，并且在操作结束时观察到第二值。 提供了一种机制，以使操作能够继续，避免致命的异常。
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公开(公告)号：US08751775B2
公开(公告)日：2014-06-10
申请号：US13452248
申请日：2012-04-20
CPC分类号： G06F9/00 , G06F9/30 , G06F9/30003 , G06F9/3004 , G06F9/3009 , G06F9/30167 , G06F9/30181 , G06F9/3834 , G06F9/44 , G06F9/4418 , G06F9/45533 , G06F12/1475
摘要： A non-quiescing key setting facility is provided that enables manipulation of storage keys to be performed without quiescing operations of other processors of a multiprocessor system. With this facility, a storage key, which is accessible by a plurality of processors of the multiprocessor system, is updated absent a quiesce of operations of the plurality of processors. Since the storage key is updated absent quiescing of other operations, the storage key may be observed by a processor as having one value at the start of an operation performed by the processor and a second value at the end of the operation. A mechanism is provided to enable the operation to continue, avoiding a fatal exception.
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