Invention Application
- Patent Title: Semiconductor package and laminated semiconductor package
- Patent Title (中): 半导体封装和层压半导体封装
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Application No.: US10528160Application Date: 2003-11-19
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Publication No.: US20060049495A1Publication Date: 2006-03-09
- Inventor: Ichiro Hazeyama , Yoshimichi Sogawa , Takao Yamazaki , Sakae Kitajo
- Applicant: Ichiro Hazeyama , Yoshimichi Sogawa , Takao Yamazaki , Sakae Kitajo
- Applicant Address: JP TOKYO
- Assignee: NEC CORPORATION
- Current Assignee: NEC CORPORATION
- Current Assignee Address: JP TOKYO
- Priority: JP2002-335855 20021120
- International Application: PCT/JP03/14731 WO 20031119
- Main IPC: H01L23/02
- IPC: H01L23/02

Abstract:
A semiconductor package has a semiconductor device chip and a flexible substrate having a thermoplastic insulating resin layer. An electrode provided on the flexible substrate is connected to a predetermined electrode of the semiconductor device chip and sealed by the thermoplastic insulating resin layer. The flexible substrate is bent and provided with electrodes on the electrode-bearing and other surfaces. The flexible substrate has multi-layered wirings. Grooves or thin layer portions having a different number of wiring layers are formed at bends of the flexible substrate or regions including the bends, thereby creating a cavity at a portion in which a semiconductor device is packaged. Then, the flexible substrate is bent at predetermined positions to form a semiconductor package which does not depend on the outer dimensions of the semiconductor device chip.
Public/Granted literature
- US07230328B2 Semiconductor package and laminated semiconductor package Public/Granted day:2007-06-12
Information query
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