公开(公告)号：US20120106085A1

公开(公告)日：2012-05-03

申请号：US13148524

申请日：2010-01-27

Applicant: Takao Yamazaki ,  Masahiko Sano ,  Seiji Kurashina

Inventor： Takao Yamazaki ,  Masahiko Sano ,  Seiji Kurashina

IPC: H05K7/20 ,  H05K7/10

CPC classification number: H05K5/066 ,  G01J5/029 ,  G01J5/045 ,  H01L23/057 ,  H01L23/10 ,  H01L23/26 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/16151 ,  H01L2924/16152 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A vacuum sealed package includes a package main body portion in which a first main body portion and a second main body portion are bonded via a hollow portion, and a getter material and an electronic device that are provided within the hollow portion, and in the state of the hollow portion being evacuated via a through-hole that brings the inside and the outside of the hollow portion into communication, the package main body portion is sealed with a sealing member, the getter material and the electronic device are connected to a first conductor pad and a second conductor pad, the first conductor pad is connected with a third conductor pad via a thermally conductive material, and the second conductor pad is electrically connected with a fourth conductor pad on a wiring substrate.

Abstract translation: 真空密封包装体包括：封装体主体部分，其中第一主体部分和第二主体部分经由中空部分接合;以及吸气材料和电子装置，其设置在中空部分内，并且处于该状态 通过使中空部的内部和外部连通的通孔而使空心部抽真空，将封装主体部用密封部件密封，吸气材料和电子装置与第一导体 焊盘和第二导体焊盘，第一导体焊盘通过导热材料与第三导体焊盘连接，并且第二导体焊盘与布线基板上的第四导体焊盘电连接。

公开(公告)号：US20120028419A1

公开(公告)日：2012-02-02

申请号：US13020410

申请日：2011-02-03

Applicant: TAKAO YAMAZAKI

Inventor： TAKAO YAMAZAKI

IPC: H01L21/50

CPC classification number: H01L23/4985 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/5387 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/81001 ,  H01L2224/81011 ,  H01L2224/8112 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/83855 ,  H01L2224/8388 ,  H01L2224/92225 ,  H01L2225/1005 ,  H01L2225/107 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3511 ,  H05K1/189 ,  H05K2201/056 ,  H05K2201/10515 ,  H05K2201/10734 ,  H01L2924/07025 ,  H01L2924/00 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/00015 ,  H01L2224/0401

Abstract: There is provided a low-cost semiconductor device that commercial and quality-assured (inspected) chip size packages can be stacked and has a small co-planarity value and a high mounting reliability. A semiconductor device in which a flexible circuit substrate is adhered to at least a part of a lateral side of a semiconductor package, and the flexible circuit substrate, which is on a side facing solder balls of the semiconductor package, is folded at a region inside of an edge of the semiconductor package (FIG. 1).

Abstract translation: 提供了一种廉价的半导体器件，可以堆叠商业和质量保证（检查）的芯片尺寸封装，并且具有小的共平面度值和高安装可靠性。 一种半导体器件，其中柔性电路基板粘附到半导体封装的横向侧的至少一部分，并且位于半导体封装的焊球侧的柔性电路基板在内部的区域内折叠 的半导体封装的边缘（图1）。

公开(公告)号：US20110304029A1

公开(公告)日：2011-12-15

申请号：US13216118

申请日：2011-08-23

Applicant: Yoshimichi Sogawa ,  Takao Yamazaki ,  Nobuaki Takahashi

Inventor： Yoshimichi Sogawa ,  Takao Yamazaki ,  Nobuaki Takahashi

IPC: H01L23/58

CPC classification number: H01L24/13 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/1319 ,  H01L2224/132 ,  H01L2224/133 ,  H01L2224/1358 ,  H01L2224/136 ,  H01L2224/16 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/351 ,  H05K1/0271 ,  H05K3/244 ,  H05K3/3436 ,  H05K2201/0212 ,  Y02P70/613 ,  H01L2924/01015 ,  H01L2924/00 ,  H01L2224/11

Abstract: A terminal pad is formed on an active surface of an LSI chip, and a composite barrier metal layer is provided over this terminal pad. In the composite barrier metal layer, a plurality of low-elasticity particles composed of a silicone resin is dispersed throughout a metal base phase composed of NiP. The composite barrier metal layer has a thickness of, e.g., 3 μm, and the low-elasticity particles have a diameter of, e.g., 1 μm. A semiconductor device is mounted on a wiring board by bonding a solder bump to the composite barrier metal layer. The low-elasticity particles are thereby allowed to deform according to the applied stress when the semiconductor device is bonded to the wiring board via the solder bump, whereby the stress can be absorbed.

Abstract translation: 在LSI芯片的有源面上形成端子焊盘，在该端子焊盘上设置复合阻挡金属层。 在复合阻挡金属层中，将由硅树脂构成的多个低弹性粒子分散在由NiP构成的金属基体相中。 复合阻挡金属层的厚度例如为3μm，低弹性颗粒的直径例如为1μm。 通过将焊料凸块粘合到复合阻挡金属层上，将半导体器件安装在布线板上。 因此，当半导体器件通过焊料凸块接合到布线板时，低弹性粒子根据施加的应力而变形，从而能够吸收应力。

公开(公告)号：US20110140264A1

公开(公告)日：2011-06-16

申请号：US13024910

申请日：2011-02-10

Applicant: TAKAO YAMAZAKI

Inventor： TAKAO YAMAZAKI

IPC: H01L23/498

CPC classification number: H01L23/4985 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/5387 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/81001 ,  H01L2224/81011 ,  H01L2224/8112 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/83855 ,  H01L2224/8388 ,  H01L2224/92225 ,  H01L2225/1005 ,  H01L2225/107 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3511 ,  H05K1/189 ,  H05K2201/056 ,  H05K2201/10515 ,  H05K2201/10734 ,  H01L2924/07025 ,  H01L2924/00 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/00015 ,  H01L2224/0401

Abstract: There is provided a low-cost semiconductor device that commercial and quality-assured (inspected) chip size packages can be stacked and has a small co-planarity value and a high mounting reliability. A semiconductor device in which a flexible circuit substrate is adhered to at least a part of a lateral side of a semiconductor package, and the flexible circuit substrate, which is on a side facing solder balls of the semiconductor package, is folded at a region inside of an edge of the semiconductor package (FIG. 1).

Abstract translation: 提供了一种廉价的半导体器件，可以堆叠商业和质量保证（检查）的芯片尺寸封装，并且具有小的共平面度值和高安装可靠性。 一种半导体器件，其中柔性电路基板粘附到半导体封装的横向侧的至少一部分，并且位于半导体封装的焊球侧的柔性电路基板在内部的区域内折叠 的半导体封装的边缘（图1）。

公开(公告)号：US20090243075A1

公开(公告)日：2009-10-01

申请号：US12409796

申请日：2009-03-24

Applicant: Shinji WATANABE ,  Takao YAMAZAKI

Inventor： Shinji WATANABE ,  Takao YAMAZAKI

IPC: H01L23/12 ,  H01L23/498

CPC classification number: H01L25/105 ,  H01L23/3128 ,  H01L23/5387 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A mounting structure comprises: at least one semiconductor device having solder bumps as outer terminals and a flexible wiring board with wiring formed thereon. The semiconductor device is structured to be wrapped by the flexible wiring board, the mounting structure is provided with outer electrodes on both sides of the flexible wiring board, one side being a side where outer terminals of the semiconductor device are formed, and the other side being an opposite side thereof. At least one wiring layer is formed on the flexible wiring board. A supporting member is provided covering side faces and a surface of the semiconductor device opposite to the side where the outer terminals are formed and protruding from the side faces of the semiconductor device and extending toward the surface on which the outer terminals are formed.

Abstract translation: 安装结构包括：至少一个具有作为外部端子的焊料凸块的半导体器件和其上形成有布线的柔性布线板。 半导体器件被构造成被柔性布线板包裹，安装结构在柔性布线板的两侧设置有外部电极，一侧是形成半导体器件的外部端子的一侧，另一侧 是相反的一面。 在柔性布线板上形成至少一个布线层。 提供了一种支撑构件，其覆盖半导体器件的与形成外部端子的侧相对的侧面和表面，并且从半导体器件的侧面突出并且朝向形成有外部端子的表面延伸。

公开(公告)号：US20090174052A1

公开(公告)日：2009-07-09

申请号：US12298285

申请日：2007-05-22

Applicant: Yoshimichi Sogawa ,  Takao Yamazaki ,  Nobuaki Takahashi

Inventor： Yoshimichi Sogawa ,  Takao Yamazaki ,  Nobuaki Takahashi

IPC: H01L23/52

CPC classification number: H01L23/49866 ,  H01L21/563 ,  H01L23/24 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0362 ,  H01L2224/03828 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05118 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/0516 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/115 ,  H01L2224/11502 ,  H01L2224/1152 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/75702 ,  H01L2224/8121 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/3512 ,  H01L2924/3651 ,  H05K3/244 ,  H05K3/3436 ,  H05K3/3463 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012

Abstract: In a conventional UBM made of, for example, Cu, Ni, or NiP, there has been a problem that when an electronic component is held in high-temperature conditions for an extended period, the barrier characteristic of the UBM is lost and the bonding strength decreases due to formation of a brittle alloy layer at a bonding interface. The present invention improves the problem of decrease in long-term connection reliability of a solder connection portion after storage at high temperatures. An electronic component comprises the electronic component includes an electrode pad formed on a substrate or a semiconductor element and a barrier metal layer formed to cover the electrode pad and the barrier metal layer comprises a CuNi alloy layer on the side opposite the side in contact with the electrode pad, the CuNi alloy layer containing 15 to 60 at % of Cu and 40 to 85 at % of Ni.

Abstract translation: 在由例如Cu，Ni或NiP制成的常规UBM中，存在如下问题：当电子部件长时间保持在高温条件下时，UBM的阻挡特性丧失， 由于在接合界面处形成脆性合金层，强度降低。 本发明改善了在高温下储存之后焊料连接部分的长期连接可靠性降低的问题。 电子部件包括电子部件，其包括形成在基板或半导体元件上的电极焊盘和形成为覆盖电极焊盘的阻挡金属层，并且阻挡金属层在与所述电极焊盘接触的一侧相反的一侧包括CuNi合金层 电极焊盘，含有15〜60at％的Cu和40〜85at％的Ni的CuNi合金层。

公开(公告)号：US07504701B2

公开(公告)日：2009-03-17

申请号：US11708142

申请日：2007-02-20

Applicant: Shigeru Moribayashi ,  Yoshiaki Morishita ,  Kowashi Taketomi ,  Takao Yamazaki ,  Shinji Watanabe ,  Ichiro Hatakeyama

Inventor： Shigeru Moribayashi ,  Yoshiaki Morishita ,  Kowashi Taketomi ,  Takao Yamazaki ,  Shinji Watanabe ,  Ichiro Hatakeyama

IPC: H01L31/00

CPC classification number: G02B6/4249 ,  G02B6/4214 ,  G02B6/4232 ,  G02B6/425 ,  G02B6/4292 ,  G02B6/43 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/12032 ,  H01S5/02248 ,  H01S5/02272 ,  H01S5/02276 ,  H01S5/02284 ,  H01S5/02292 ,  H01S5/183 ,  H01L2924/00

Abstract: In an optical unit including a photoelectric conversion chip adapted to be optically connected to an optical fiber, and a semiconductor chip for driving the photoelectric conversion chip, both the photoelectric conversion chip and the semiconductor chip are wrapped with a flexible sheet, to thereby produce an enveloper enveloping the photoelectric conversion chip and the semiconductor chip therein. At least a part of the enveloper is formed as a transparent area for allowing an optical connection between the optical fiber and the photoelectric conversion chip.

Abstract translation: 在包括适于与光纤光学连接的光电转换芯片的光学单元和用于驱动光电转换芯片的半导体芯片中，光电转换芯片和半导体芯片都用柔性片包裹，从而产生 封装光电转换芯片和其中的半导体芯片。 至少一部分加热器形成为允许光纤和光电转换芯片之间的光学连接的透明区域。

公开(公告)号：US07426462B2

公开(公告)日：2008-09-16

申请号：US10674980

申请日：2003-09-29

Applicant: Jeongnam Young ,  Sundararam Dwarakanath ,  Cheung Auyeung ,  Takao Yamazaki

Inventor： Jeongnam Young ,  Sundararam Dwarakanath ,  Cheung Auyeung ,  Takao Yamazaki

IPC: G10L19/00

CPC classification number: H03M7/42 ,  G10L19/04 ,  G10L2019/0013

Abstract: The largest absolute value (LAV) is determined within a group of data. Based on the LAV, a difference table is identified that is to be used for selecting an optimal Huffman codebook for the group of data. The difference table is associated with two Huffman codebooks. Further, one or more indexes are calculated for the group of data using an expression associated with the two Huffman codebooks, and a size difference value is determined for the group of data using the calculated indexes and the difference table. Based on the determined size difference value, the optimal Huffman codebook is selected from the above two codebooks.

Abstract translation: 在一组数据内确定最大绝对值（LAV）。 基于LAV，识别出用于为数据组选择最佳霍夫曼码本的差异表。 差异表与两个霍夫曼代码簿相关联。 此外，使用与两个霍夫曼码本相关联的表达式针对数据组计算一个或多个索引，并且使用所计算的索引和差异表来确定数据组的大小差值。 基于确定的尺寸差值，从上述两个码本中选择最佳霍夫曼码本。

公开(公告)号：US20080001288A1

公开(公告)日：2008-01-03

申请号：US11720066

申请日：2005-11-25

Applicant: Yoshimichi Sogawa ,  Takao Yamazaki ,  Nobuaki Takahashi

Inventor： Yoshimichi Sogawa ,  Takao Yamazaki ,  Nobuaki Takahashi

IPC: H01L23/52 ,  H01L21/4763 ,  H01L23/48

CPC classification number: H01L24/13 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/1319 ,  H01L2224/132 ,  H01L2224/133 ,  H01L2224/1358 ,  H01L2224/136 ,  H01L2224/16 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/351 ,  H05K1/0271 ,  H05K3/244 ,  H05K3/3436 ,  H05K2201/0212 ,  Y02P70/613 ,  H01L2924/01015 ,  H01L2924/00 ,  H01L2224/11

Abstract: A terminal pad is formed on an active surface of an LSI chip, and a composite barrier metal layer is provided over this terminal pad. In the composite barrier metal layer, a plurality of low-elasticity particles composed of a silicone resin is dispersed throughout a metal base phase composed of NiP. The composite barrier metal layer has a thickness of, e.g., 3 μm, and the low-elasticity particles have a diameter of, e.g., 1 μm. A semiconductor device is mounted on a wiring board by bonding a solder bump to the composite barrier metal layer. The low-elasticity particles are thereby allowed to deform according to the applied stress when the semiconductor device is bonded to the wiring board via the solder bump, whereby the stress can be absorbed.

Abstract translation: 在LSI芯片的有源面上形成端子焊盘，在该端子焊盘上设置复合阻挡金属层。 在复合阻挡金属层中，将由硅树脂构成的多个低弹性粒子分散在由NiP构成的金属基体相中。 复合阻挡金属层具有例如3μm的厚度，低弹性颗粒的直径例如为1μm。 通过将焊料凸块粘合到复合阻挡金属层上，将半导体器件安装在布线板上。 因此，当半导体器件通过焊料凸块接合到布线板时，低弹性粒子根据施加的应力而变形，从而能够吸收应力。

公开(公告)号：US20060049495A1

公开(公告)日：2006-03-09

申请号：US10528160

申请日：2003-11-19

Applicant: Ichiro Hazeyama ,  Yoshimichi Sogawa ,  Takao Yamazaki ,  Sakae Kitajo

Inventor： Ichiro Hazeyama ,  Yoshimichi Sogawa ,  Takao Yamazaki ,  Sakae Kitajo

IPC: H01L23/02

CPC classification number: H01L23/3114 ,  H01L23/5387 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2924/00

Abstract: A semiconductor package has a semiconductor device chip and a flexible substrate having a thermoplastic insulating resin layer. An electrode provided on the flexible substrate is connected to a predetermined electrode of the semiconductor device chip and sealed by the thermoplastic insulating resin layer. The flexible substrate is bent and provided with electrodes on the electrode-bearing and other surfaces. The flexible substrate has multi-layered wirings. Grooves or thin layer portions having a different number of wiring layers are formed at bends of the flexible substrate or regions including the bends, thereby creating a cavity at a portion in which a semiconductor device is packaged. Then, the flexible substrate is bent at predetermined positions to form a semiconductor package which does not depend on the outer dimensions of the semiconductor device chip.

Abstract translation: 半导体封装具有半导体器件芯片和具有热塑性绝缘树脂层的柔性基板。 设置在柔性基板上的电极连接到半导体器件芯片的预定电极并被热塑性绝缘树脂层密封。 柔性基板弯曲并在电极轴承和其它表面上设置电极。 柔性基板具有多层布线。 在柔性基板或弯曲部的区域的弯曲处形成具有不同数量的布线层的沟槽或薄层部分，从而在半导体器件被封装的部分形成空腔。 然后，柔性基板在预定位置弯曲以形成不依赖于半导体器件芯片的外部尺寸的半导体封装。