发明申请
- 专利标题: IEEE Std. 1149.4 compatible analog BIST methodology
- 专利标题(中): IEEE标准 1149.4兼容模拟BIST方法
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申请号: US11211092申请日: 2005-08-25
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公开(公告)号: US20060059395A1公开(公告)日: 2006-03-16
- 发明人: Chauchin Su , Shyh-Horng Lin , Laung-Terng Wang
- 申请人: Chauchin Su , Shyh-Horng Lin , Laung-Terng Wang
- 主分类号: G01R31/28
- IPC分类号: G01R31/28
摘要:
An analog built-in self-test (BIST) methodology based on the IEEE 1149.4 mixed signal test bus standard. The on-chip generated triangular stimuli are transmitted to the analog circuit under test (CUT) through the analog test buses, and their test responses are quantized by the dual comparators. The quantized results are then fed into a pair of counters to record the sampled counts for comparison in the decision circuit. A pass/fail indication is then generated in the decision circuit to indicate success or failure of the CUT after the BIST operation is complete.
公开/授权文献
- US07228479B2 IEEE Std. 1149.4 compatible analog BIST methodology 公开/授权日:2007-06-05
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