公开(公告)号：US07764086B2

公开(公告)日：2010-07-27

申请号：US11853003

申请日：2007-09-10

申请人： Hung Wen Lu ,  Chauchin Su

发明人： Hung Wen Lu ,  Chauchin Su

IPC分类号： H03K19/0175 ,  H03K3/00 ,  H03K3/289

CPC分类号： H03K19/018571 ,  H03K19/00323 ,  H03K19/01707 ,  H04L25/0272 ,  H04L25/028

摘要： A buffer circuit having an input terminal and an output terminal comprises a first inverter having an input node coupled to the input terminal and an output node coupled to the output terminal, a second inverter having an input node coupled to a reference voltage and an output node, a third inverter having an input node coupled to the output terminal and an output node coupled to the output node of the second inverter, a fourth inverter having an input node coupled to the output node of the second inverter and an output node coupled to the output terminal, a fifth inverter having an input node and an output node coupled to the output terminal, a sixth inverter having an input node and an output node coupled to the output node of the second inverter, a first resistive element is coupled between the output terminal and the input node of the fifth inverter, and a second resistive element is coupled between the output node of the second inverter and the input node of the sixth inverter.

摘要翻译： 具有输入端和输出端的缓冲电路包括具有耦合到输入端的输入节点和耦合到输出端的输出节点的第一反相器，具有耦合到参考电压的输入节点的第二反相器和输出节点 具有耦合到所述输出端的输入节点和耦合到所述第二反相器的输出节点的输出节点的第三反相器，具有耦合到所述第二反相器的输出节点的输入节点的第四反相器和耦合到所述第二反相器的输出节点的输出节点 输出端子，具有输入节点和耦合到输出端子的输出节点的第五反相器，具有耦合到第二反相器的输出节点的输入节点和输出节点的第六反相器，第一电阻元件耦合在输出端 端子和第五反相器的输入节点，第二电阻元件耦合在第二反相器的输出节点和第六反相器的输入节点之间。

公开(公告)号：US08806414B2

公开(公告)日：2014-08-12

申请号：US13484480

申请日：2012-05-31

申请人： Mu-Jen Huang ,  Yu-Sian Jiang ,  Yi-Ting Lin ,  Hsien-Yu Tseng ,  Heng Kai Liu ,  Chien-Wen Chen ,  Chauchin Su

发明人： Mu-Jen Huang ,  Yu-Sian Jiang ,  Yi-Ting Lin ,  Hsien-Yu Tseng ,  Heng Kai Liu ,  Chien-Wen Chen ,  Chauchin Su

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F2217/82

摘要： A system comprises an electronic design automation (EDA) tool, for generating a schematic design of an integrated circuit (IC), generating a layout from the schematic design, editing the layout, and verifying the schematic design and layout. At least one non-transitory, computer readable storage medium, is provided for storing data representing the schematic design and the layout, the layout having a network of routing paths connecting at least two active layer devices of the IC design. An RC tool is provided for computing estimated parasitic capacitances of the routing paths of the network before verifying the schematic design and layout, and for inserting a capacitor corresponding to the estimated parasitic capacitance into the data representing the schematic design of the IC. A first device level simulation tool for simulating performance of the network based on the at least two active layer devices and the estimated parasitic capacitances.

摘要翻译： 一种系统包括电子设计自动化（EDA）工具，用于产生集成电路（IC）的示意性设计，从原理图设计生成布局，编辑布局以及验证原理图设计和布局。 提供了至少一个非暂时的计算机可读存储介质，用于存储表示示意图设计和布局的数据，该布局具有连接IC设计的至少两个有源层设备的路由路径网络。 提供了一种RC工具，用于在验证原理图设计和布局之前计算网络路由路径的估计寄生电容，并将与估计的寄生电容对应的电容插入到表示IC原理图设计的数据中。 用于基于至少两个有源层器件和估计的寄生电容来模拟网络的性能的第一器件级仿真工具。

公开(公告)号：US08726207B2

公开(公告)日：2014-05-13

申请号：US13115752

申请日：2011-05-25

申请人： Yu-Sian Jiang ,  Ya-Li Tai ,  Mu-Jen Huang ,  Chien-Wen Chen ,  Chauchin Su

发明人： Yu-Sian Jiang ,  Ya-Li Tai ,  Mu-Jen Huang ,  Chien-Wen Chen ,  Chauchin Su

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A design system includes a layout module and a user interface. The layout module includes a computing unit, which is configured to extract layout parameters of an integrated circuit device in a circuit during a layout stage of the circuit, and calculate circuit parameters of the device using the layout parameters. The user interface is configured to display the circuit parameters of the device in response to a user selection of the device.

摘要翻译： 设计系统包括布局模块和用户界面。 布局模块包括计算单元，其被配置为在电路的布局阶段期间提取电路中的集成电路器件的布局参数，并且使用布局参数来计算器件的电路参数。 用户界面被配置为响应于用户对设备的选择来显示设备的电路参数。

公开(公告)号：US20120304146A1

公开(公告)日：2012-11-29

申请号：US13115752

申请日：2011-05-25

申请人： Yu-Sian Jiang ,  Ya-Li Tai ,  Mu-Jen Huang ,  Chien-Wen Chen ,  Chauchin Su

发明人： Yu-Sian Jiang ,  Ya-Li Tai ,  Mu-Jen Huang ,  Chien-Wen Chen ,  Chauchin Su

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A design system includes a layout module and a user interface. The layout module includes a computing unit, which is configured to extract layout parameters of an integrated circuit device in a circuit during a layout stage of the circuit, and calculate circuit parameters of the device using the layout parameters. The user interface is configured to display the circuit parameters of the device in response to a user selection of the device.

摘要翻译： 设计系统包括布局模块和用户界面。 布局模块包括计算单元，其被配置为在电路的布局阶段期间提取电路中的集成电路器件的布局参数，并且使用布局参数来计算器件的电路参数。 用户界面被配置为响应于用户对设备的选择来显示设备的电路参数。

公开(公告)号：US20080150583A1

公开(公告)日：2008-06-26

申请号：US11853003

申请日：2007-09-10

申请人： Hung Wen LU ,  Chauchin SU

发明人： Hung Wen LU ,  Chauchin SU

IPC分类号： H03K19/0175 ,  H03K19/094

CPC分类号： H03K19/018571 ,  H03K19/00323 ,  H03K19/01707 ,  H04L25/0272 ,  H04L25/028

摘要： A buffer circuit having an input terminal and an output terminal comprises a first inverter having an input node coupled to the input terminal and an output node coupled to the output terminal, a second inverter having an input node coupled to a reference voltage and an output node, a third inverter having an input node coupled to the output terminal and an output node coupled to the output node of the second inverter, a fourth inverter having an input node coupled to the output node of the second inverter and an output node coupled to the output terminal, a fifth inverter having an input node and an output node coupled to the output terminal, a sixth inverter having an input node and an output node coupled to the output node of the second inverter, a first resistive element is coupled between the output terminal and the input node of the fifth inverter, and a second resistive element is coupled between the output node of the second inverter and the input node of the sixth inverter.

摘要翻译： 具有输入端和输出端的缓冲电路包括具有耦合到输入端的输入节点和耦合到输出端的输出节点的第一反相器，具有耦合到参考电压的输入节点的第二反相器和输出节点 具有耦合到所述输出端的输入节点和耦合到所述第二反相器的输出节点的输出节点的第三反相器，具有耦合到所述第二反相器的输出节点的输入节点的第四反相器和耦合到所述第二反相器的输出节点的输出节点 输出端子，具有输入节点和耦合到输出端子的输出节点的第五反相器，具有耦合到第二反相器的输出节点的输入节点和输出节点的第六反相器，第一电阻元件耦合在输出端 端子和第五反相器的输入节点，第二电阻元件耦合在第二反相器的输出节点和第六反相器的输入节点之间。

公开(公告)号：US20060059395A1

公开(公告)日：2006-03-16

申请号：US11211092

申请日：2005-08-25

申请人： Chauchin Su ,  Shyh-Horng Lin ,  Laung-Terng Wang

发明人： Chauchin Su ,  Shyh-Horng Lin ,  Laung-Terng Wang

IPC分类号： G01R31/28

CPC分类号： G01R31/2884 ,  G01R31/3167

摘要： An analog built-in self-test (BIST) methodology based on the IEEE 1149.4 mixed signal test bus standard. The on-chip generated triangular stimuli are transmitted to the analog circuit under test (CUT) through the analog test buses, and their test responses are quantized by the dual comparators. The quantized results are then fed into a pair of counters to record the sampled counts for comparison in the decision circuit. A pass/fail indication is then generated in the decision circuit to indicate success or failure of the CUT after the BIST operation is complete.

摘要翻译： 基于IEEE 1149.4混合信号测试总线标准的模拟内置自检（BIST）方法。 片上产生的三角刺激通过模拟测试总线传输到被测模拟电路（CUT），它们的测试响应由双比较器进行量化。 然后将量化的结果馈送到一对计数器中以记录在判定电路中进行比较的采样计数。 然后在判定电路中产生通过/失败指示，以指示BIST操作完成后CUT的成功或失败。

公开(公告)号：US20130326447A1

公开(公告)日：2013-12-05

申请号：US13484480

申请日：2012-05-31

申请人： Mu-Jen HUANG ,  Yu-Sian JIANG ,  Yi-Ting LIN ,  Hsien-Yu TSENG ,  Heng Kai LIU ,  Chien-Wen CHEN ,  Chauchin SU

发明人： Mu-Jen HUANG ,  Yu-Sian JIANG ,  Yi-Ting LIN ,  Hsien-Yu TSENG ,  Heng Kai LIU ,  Chien-Wen CHEN ,  Chauchin SU

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F2217/82

摘要： A system comprises an electronic design automation (EDA) tool, for generating a schematic design of an integrated circuit (IC), generating a layout from the schematic design, editing the layout, and verifying the schematic design and layout. At least one non-transitory, computer readable storage medium, is provided for storing data representing the schematic design and the layout, the layout having a network of routing paths connecting at least two active layer devices of the IC design. An RC tool is provided for computing estimated parasitic capacitances of the routing paths of the network before verifying the schematic design and layout, and for inserting a capacitor corresponding to the estimated parasitic capacitance into the data representing the schematic design of the IC. A first device level simulation tool for simulating performance of the network based on the at least two active layer devices and the estimated parasitic capacitances.

摘要翻译： 一种系统包括电子设计自动化（EDA）工具，用于产生集成电路（IC）的示意性设计，从原理图设计生成布局，编辑布局以及验证原理图设计和布局。 提供了至少一个非暂时的计算机可读存储介质，用于存储表示示意图设计和布局的数据，该布局具有连接IC设计的至少两个有源层设备的路由路径网络。 提供了一种RC工具，用于在验证原理图设计和布局之前计算网络路由路径的估计寄生电容，并将与估计的寄生电容对应的电容插入到表示IC原理图设计的数据中。 用于基于至少两个有源层器件和估计的寄生电容来模拟网络的性能的第一器件级仿真工具。

公开(公告)号：US07228479B2

公开(公告)日：2007-06-05

申请号：US11211092

申请日：2005-08-25

申请人： Chauchin Su ,  Shyh-Horng Lin ,  Laung-Terng (L.-T.) Wang

发明人： Chauchin Su ,  Shyh-Horng Lin ,  Laung-Terng (L.-T.) Wang

IPC分类号： G01R31/28

CPC分类号： G01R31/2884 ,  G01R31/3167

摘要： An analog built-in self-test (BIST) methodology based on the IEEE 1149.4 mixed signal test bus standard. The on-chip generated triangular stimuli are transmitted to the analog circuit under test (CUT) through the analog test buses, and their test responses are quantized by the dual comparators. The quantized results are then fed into a pair of counters to record the sampled counts for comparison in the decision circuit. A pass/fail indication is then generated in the decision circuit to indicate success or failure of the CUT after the BIST operation is complete.

摘要翻译： 基于IEEE 1149.4混合信号测试总线标准的模拟内置自检（BIST）方法。 片上产生的三角刺激通过模拟测试总线传输到被测模拟电路（CUT），它们的测试响应由双比较器进行量化。 然后将量化的结果馈送到一对计数器中以记录在判定电路中进行比较的采样计数。 然后在判定电路中产生通过/失败指示，以指示BIST操作完成后CUT的成功或失败。