Invention Application
- Patent Title: Three dimensional package and packaging method for integrated circuits
- Patent Title (中): 集成电路的三维封装和封装方法
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Application No.: US10953045Application Date: 2004-09-29
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Publication No.: US20060065958A1Publication Date: 2006-03-30
- Inventor: Pei-Haw Tsao , Chao-Yuan Su , Allan Lin , Frank Wu , Chender Huang
- Applicant: Pei-Haw Tsao , Chao-Yuan Su , Allan Lin , Frank Wu , Chender Huang
- Main IPC: H01L23/495
- IPC: H01L23/495
Abstract:
A 3D package has: a three-dimensional (3D) package substrate, a land grid array (LGA) or quad flat no-lead (QFN) package mounted on the 3D package substrate, the LGA or QFN package having an LGA or QFN die on a first side of an LGA or QFN package substrate, and a second die mounted directly on a second side of the LGA or QFN package substrate opposite the first side.
Information query
IPC分类:
