公开(公告)号：US20110057313A1

公开(公告)日：2011-03-10

申请号：US12899168

申请日：2010-10-06

申请人： Kuo-Chin Chang ,  Han-Ping Pu ,  Pei-Haw Tsao

发明人： Kuo-Chin Chang ,  Han-Ping Pu ,  Pei-Haw Tsao

IPC分类号： H01L23/498

CPC分类号： H01L24/11 ,  H01L24/81 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/114 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/116 ,  H01L2224/11902 ,  H01L2224/13019 ,  H01L2224/13076 ,  H01L2224/13078 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/81801 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00

摘要： An enhanced wafer level chip scale packaging (WLCSP) copper electrode post is described having one or more pins that protrude from the top of the electrode post. When the solder ball is soldered onto the post, the pins are encapsulated within the solder material. The pins not only add shear strength to the soldered joint between the solder ball and the electrode post but also create a more reliable electrical connection due to the increased surface area between the electrode post/pin combination and the solder ball. Moreover, creating an irregularly shaped solder joint retards the propagation of cracks that may form in the intermetal compounds (IMC) layer formed at the solder joint.

摘要翻译： 描述了增强的晶片级芯片级封装（WLCSP）铜电极柱，其具有从电极柱的顶部突出的一个或多个引脚。 当焊球焊接到柱上时，引脚被封装在焊料材料内。 引脚不仅在焊球和电极柱之间的焊接接头上增加剪切强度，而且由于电极柱/销组合和焊球之间的表面积增加，也产生更可靠的电连接。 此外，产生不规则形状的焊点阻碍了可能在焊接接头形成的金属间化合物（IMC）层中形成的裂纹的传播。

公开(公告)号：US07843058B2

公开(公告)日：2010-11-30

申请号：US11928971

申请日：2007-10-30

申请人： Pei-Haw Tsao ,  Liang-Chen Lin ,  Pao-Kang Niu

发明人： Pei-Haw Tsao ,  Liang-Chen Lin ,  Pao-Kang Niu

IPC分类号： H01L23/34

CPC分类号： H01L23/4006 ,  H01L23/42 ,  H01L23/433 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/00012 ,  H01L2924/00

摘要： A package structure includes a substrate; a die over and flip bonded on the substrate; a heat sink over the die; and one or more spacer separating the heat sink from the substrate.

摘要翻译： 封装结构包括基板; 在基板上切割并翻转接合; 模具上的散热片; 以及将散热器与衬底分隔开的一个或多个间隔件。

公开(公告)号：US20100187687A1

公开(公告)日：2010-07-29

申请号：US12619503

申请日：2009-11-16

申请人： Yu-Wen Liu ,  Hao-Yi Tsai ,  Hsien-Wei Chen ,  Shin-Puu Jeng ,  Ying-Ju Chen ,  Shang-Yun Hou ,  Pei-Haw Tsao ,  Chen-Hua Yu

发明人： Yu-Wen Liu ,  Hao-Yi Tsai ,  Hsien-Wei Chen ,  Shin-Puu Jeng ,  Ying-Ju Chen ,  Shang-Yun Hou ,  Pei-Haw Tsao ,  Chen-Hua Yu

IPC分类号： H01L23/488 ,  H01L21/60

CPC分类号： H01L24/05 ,  H01L23/3157 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/0215 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05096 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05541 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05566 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13007 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/00014 ,  H01L2924/2064 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599

摘要： A system and method for forming an underbump metallization (UBM) is presented. A preferred embodiment includes a raised UBM which extends through a passivation layer so as to make contact with a contact pad while retaining enough of the passivation layer between the contact pad and the UBM to adequately handle the peeling and shear stress that results from CTE mismatch and subsequent thermal processing. The UBM contact is preferably formed in either an octagonal ring shape or an array of contacts.

摘要翻译： 提出了一种用于形成底部金属化（UBM）的系统和方法。 优选实施例包括凸起的UBM，其延伸穿过钝化层以便与接触焊盘接触，同时在接触焊盘和UBM之间保留足够的钝化层以充分地处理由CTE失配引起的剥离和剪切应力， 后续热处理。 UBM触点优选地形成为八边形环形或触点阵列。

公开(公告)号：US07662665B2

公开(公告)日：2010-02-16

申请号：US11655844

申请日：2007-01-22

申请人： Chen-Shien Chen ,  Kuo-Chin Chang ,  Szu-Wei Lu ,  Pei-Haw Tsao ,  Chung-Yu Wang ,  Han-Liang Tseng ,  Mirng-Ji Lii

发明人： Chen-Shien Chen ,  Kuo-Chin Chang ,  Szu-Wei Lu ,  Pei-Haw Tsao ,  Chung-Yu Wang ,  Han-Liang Tseng ,  Mirng-Ji Lii

IPC分类号： H01L21/00

CPC分类号： H01L23/49816 ,  H01L21/4853 ,  H01L23/49827 ,  H01L24/02 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/02319 ,  H01L2224/02321 ,  H01L2224/0401 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00

摘要： A method for fabricating a semiconductor package is provided. In one embodiment, a semiconductor chip having a plurality of exposed conductive layers thereon is provided. A first substrate having a first surface and a second surface is provided, the first surface having a plurality of exposed via plugs thereunder. The semiconductor chip is bonded to the first substrate, wherein the plurality of exposed conductor layers are aligned and in contact with the surfaces of the exposed via plugs. A portion of the second surface of the first substrate is then removed to expose the opposite ends of the plurality of via plugs. A plurality of UBM layers is formed on the surfaces of the opposite ends of the plurality of via plugs. A plurality of solder bumps is formed and mounted on the UBM layers. A second substrate having a first surface and a second surface is provided, the solder bumps being mounted to the first surface of the second substrate. A plurality of solder balls is formed and mounted to the second surface of the second substrate. A third substrate is mounted to the solder balls.

摘要翻译： 提供一种制造半导体封装的方法。 在一个实施例中，提供其上具有多个暴露的导电层的半导体芯片。 提供具有第一表面和第二表面的第一基底，所述第一表面在其下具有多个暴露的通孔塞。 半导体芯片被接合到第一基板，其中多个暴露的导体层被对准并且与暴露的通孔塞的表面接触。 然后去除第一基板的第二表面的一部分以暴露多个通孔塞的相对端。 在多个通孔塞的相对端的表面上形成多个UBM层。 多个焊料凸起形成并安装在UBM层上。 提供具有第一表面和第二表面的第二基底，焊料凸块安装到第二基底的第一表面。 多个焊球形成并安装在第二基板的第二表面上。 第三衬底安装到焊球。

公开(公告)号：US07583502B2

公开(公告)日：2009-09-01

申请号：US11423745

申请日：2006-06-13

申请人： Pei-Haw Tsao ,  Hsin-Yu Pan

发明人： Pei-Haw Tsao ,  Hsin-Yu Pan

IPC分类号： H05K7/20

CPC分类号： H01L23/467 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/15311

摘要： A heat sink is presented for dissipating heat from an integrated circuit (IC). The heat sink is made of a heat conductive material having a generally planar shape and adapted to receive an IC chip on a bottom surface and adapted to be in thermal connection with the IC chip. The heat sink has a plurality of fins extending from and above a top surface of the heat sink and a plurality of slots providing fluid communication between the top surface and the bottom surface. The plurality of slots allow for air circulation below the heat sink and around the IC and other proximate components to increase heat dissipation.

摘要翻译： 提供散热器用于散热集成电路（IC）的热量。 散热器由具有大致平面形状的导热材料制成，并且适于在底表面上容纳IC芯片并适于与IC芯片热连接。 散热器具有从散热器的顶表面上方和上方延伸的多个翅片，以及多个槽，其在顶表面和底表面之间提供流体连通。 多个狭槽允许在散热器下面以及IC和其他附近部件周围的空气循环以增加散热。

公开(公告)号：US20080169557A1

公开(公告)日：2008-07-17

申请号：US11652086

申请日：2007-01-11

申请人： Pei-Haw Tsao ,  Bill Kiang ,  Liang-Chen Lin ,  Pao-Kang Niu ,  I-Tai Liu

发明人： Pei-Haw Tsao ,  Bill Kiang ,  Liang-Chen Lin ,  Pao-Kang Niu ,  I-Tai Liu

IPC分类号： H01L23/34

CPC分类号： H01L25/0657 ,  H01L21/563 ,  H01L23/3128 ,  H01L24/28 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/16225 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29298 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48475 ,  H01L2224/4848 ,  H01L2224/48499 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/8385 ,  H01L2224/85051 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/3512 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/0401 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A system-in-package (SiP) package is provided. In one embodiment, the SiP package comprises a substrate having a first surface and a second surface opposite the first surface, the substrate having a set of bond wire studs on bond pads formed on the second surface thereof; a first semiconductor chip having a first surface and a second surface opposite the first surface, wherein the first surface of the first semiconductor chip is mounted to the second surface of the substrate by means of solder bumps; an underfill material disposed between the first semiconductor chip and the substrate, encapsulating the solder bumps; a second semiconductor chip having a first surface and a second surface opposite the first surface, wherein the first surface of the second semiconductor chip is mounted to the second surface of the first semiconductor chip; and a set of bond wires electrically coupled from the second semiconductor chip to the set of bond wire studs on the substrate.

摘要翻译： 提供系统级封装（SiP）封装。 在一个实施例中，SiP封装包括具有第一表面和与第一表面相对的第二表面的衬底，衬底在其第二表面上形成的接合焊盘上具有一组接合线柱; 第一半导体芯片，具有与第一表面相对的第一表面和第二表面，其中第一半导体芯片的第一表面通过焊料凸块安装到基板的第二表面; 设置在所述第一半导体芯片和所述基板之间的底部填充材料，封装所述焊料凸块; 第二半导体芯片，具有与第一表面相对的第一表面和第二表面，其中第二半导体芯片的第一表面安装到第一半导体芯片的第二表面; 以及从第二半导体芯片电耦合到衬底上的一组接合线柱的一组接合线。

公开(公告)号：US07378731B2

公开(公告)日：2008-05-27

申请号：US11705130

申请日：2007-02-12

申请人： Chender Huang ,  Pei-Haw Tsao ,  Allan Lin ,  Jeffrey Hsu

发明人： Chender Huang ,  Pei-Haw Tsao ,  Allan Lin ,  Jeffrey Hsu

IPC分类号： H01L23/10

CPC分类号： H01L23/36 ,  H01L23/3128 ,  H01L23/4334 ,  H01L24/45 ,  H01L24/48 ,  H01L24/81 ,  H01L2224/16 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/05599 ,  H01L2224/0401 ,  H01L2924/00012

摘要： A heat spreader and package structure utilizing the same. The heat spreader is embedded in an encapsulant of a package and above a chip therein, wherein the package has a substrate, having a molding gate, and the chip has a center and a corner which is the farthest from the molding gate. The spreader includes a base with a hollow portion therethrough, a plurality of support leads, protruding from the base, on the inner edge, and a cap plate, having a hole at least directly above a region between the center and the corner of the chip, fixed by the support leads to be above the hollow portion, the cap plate.

摘要翻译： 散热器和利用其的包装结构。 散热器嵌入在封装的密封剂中并且在其中的芯片之上，其中封装具有具有模制浇口的基板，并且芯片具有与模制浇口最远的中心和拐角。 吊具包括具有穿过其的中空部分的基部，在内边缘上从基部突出的多个支撑引线和盖板，其具有至少直接在芯片的中心和拐角之间的区域上方的孔 通过支撑件固定在中空部分上方的盖板上。

公开(公告)号：US20080003803A1

公开(公告)日：2008-01-03

申请号：US11477933

申请日：2006-06-30

申请人： Pei-Haw Tsao ,  Pao-Kang Niu ,  D. J. Perng

发明人： Pei-Haw Tsao ,  Pao-Kang Niu ,  D. J. Perng

IPC分类号： H01L21/44 ,  H01L27/082 ,  H01L27/102

CPC分类号： H01L24/10 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/0558 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/05676 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/351 ,  H05K1/112 ,  H05K3/28 ,  H05K3/3436 ,  H05K2201/09436 ,  H05K2201/09472 ,  H05K2201/09509 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/013

摘要： A method for forming a semiconductor package is provided. In one embodiment, the method comprises providing a semiconductor substrate having at least one bump pad formed thereon. A solder mask layer is provided above the bump pad, the solder mask layer having at least one opening formed therein exposing a portion of the bump pad. A layer of solder wettable material is formed on the exposed surface of the bump pad and the sidewalls and substantially on the comers of the solder mask layer. A solder material is deposited above the layer of solder wettable material and portions of the solder mask layer and the solder material is reflown to create a solder bump.

摘要翻译： 提供一种形成半导体封装的方法。 在一个实施例中，该方法包括提供其上形成有至少一个凸块焊盘的半导体衬底。 焊料掩模层设置在凸块焊盘的上方，焊料掩模层具有形成在其中的至少一个开口，露出凸块焊盘的一部分。 焊料可润湿材料层形成在凸块焊盘的暴露表面和基本上在焊料掩模层的侧壁上。 在焊料可润湿材料层之上沉积焊料材料，并且焊料掩模层和焊料材料的部分被反驳以产生焊料凸点。

公开(公告)号：US07190066B2

公开(公告)日：2007-03-13

申请号：US11073676

申请日：2005-03-08

申请人： Chender Huang ,  Pei-Haw Tsao ,  Allan Lin ,  Jeffrey Hsu

发明人： Chender Huang ,  Pei-Haw Tsao ,  Allan Lin ,  Jeffrey Hsu

IPC分类号： H01L23/12

CPC分类号： H01L23/36 ,  H01L23/3128 ,  H01L23/4334 ,  H01L24/45 ,  H01L24/48 ,  H01L24/81 ,  H01L2224/16 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/05599 ,  H01L2224/0401 ,  H01L2924/00012

摘要： A heat spreader and package structure utilizing the same. The heat spreader is embedded in an encapsulant of a package and above a chip therein, wherein the package has a substrate, having a molding gate, and the chip has a center and a corner which is the farthest from the molding gate. The spreader includes a base with a hollow portion therethrough, a plurality of support leads, protruding from the base, on the inner edge, and a cap plate, having a hole at least directly above a region between the center and the corner of the chip, fixed by the support leads to be above the hollow portion, the cap plate.

公开(公告)号：US07157734B2

公开(公告)日：2007-01-02

申请号：US10908839

申请日：2005-05-27

申请人： Pei-Haw Tsao ,  Chender Huang ,  Shang-Yu Hou ,  Chao-Yuan Su ,  Chia-Hsiung Hsu

发明人： Pei-Haw Tsao ,  Chender Huang ,  Shang-Yu Hou ,  Chao-Yuan Su ,  Chia-Hsiung Hsu

IPC分类号： H01L23/58

CPC分类号： H01L24/05 ,  H01L22/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4807 ,  H01L2224/48091 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2224/48824 ,  H01L2924/00 ,  H01L2224/48744

摘要： Described is a semiconductor device having improved semiconductor bond pad reliability and methods of manufacturing thereof. The semiconductor device includes a layer formed over an integrated circuit on a semiconductor substrate. The first layer includes a conductive portion and an insulating portion. A second layer is then formed over the first layer and includes a conductive portion corresponding to the first layer's conductive portion and an insulating portion corresponding to the first layer's insulating portion. A bond pad is then formed over the first and second layers such that the bond pad is substantially situated above the conductive portions and the insulating portions of the first and second layers. A bonding ball is then formed on the bond pad substantially above the conduction portion of the first and second layers.

摘要翻译： 描述了具有改进的半导体接合焊盘可靠性的半导体器件及其制造方法。 半导体器件包括在半导体衬底上的集成电路上形成的层。 第一层包括导电部分和绝缘部分。 然后在第一层上形成第二层，并且包括对应于第一层导电部分的导电部分和对应于第一层绝缘部分的绝缘部分。 然后在第一层和第二层上形成接合焊盘，使得接合焊盘基本上位于第一层和第二层的导电部分和绝缘部分之上。 然后在接合焊盘上形成基本上在第一和第二层的导电部分上方的接合球。