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11 条记录 (耗时 0.022 秒)

    Method for Multiple Touch Control Virtual Objects and System thereof
    8.
    发明申请
    Method for Multiple Touch Control Virtual Objects and System thereof 审中-公开
    多触摸控制虚拟对象及其系统的方法

    公开(公告)号：US20130127745A1

    公开(公告)日：2013-05-23

    申请号：US13473994

    申请日：2012-05-17

    申请人： Po-Tsang Li ,  Yao-Sheng Yeh ,  Ming-Hsun Chen ,  Jing-Ru Chiu ,  Yi-Yuan Li ,  Kuan-Chu Hou ,  Pei-Zhen Lin ,  Wei-Chien Tsai ,  Allan Lin ,  Wen-Lung Tsai ,  Chung-Ming Lin

    发明人： Po-Tsang Li ,  Yao-Sheng Yeh ,  Ming-Hsun Chen ,  Jing-Ru Chiu ,  Yi-Yuan Li ,  Kuan-Chu Hou ,  Pei-Zhen Lin ,  Wei-Chien Tsai ,  Allan Lin ,  Wen-Lung Tsai ,  Chung-Ming Lin

    IPC分类号： G06F3/041

    CPC分类号： G06F3/04886

    摘要： A multi-user operating system through a multi-touch panel comprises a processor; a storage medium coupled to the processor; a multiple touch panel coupled to the processor to sense multi-touch event by at least one user, followed by displaying instruction result corresponding to the multi-touch event; a display dividing module coupled to the processor to divide the multiple touch panel into at least two sub-display areas; multiple user operation module being stored in the storage medium to instruct the display dividing module to execute a multiple user mode or a single user mode, thereby allowing the multiple user manipulate virtual objects on the at least two sub-display areas, simultaneously.

    摘要翻译： 通过多触摸面板的多用户操作系统包括处理器; 耦合到所述处理器的存储介质; 耦合到所述处理器以由至少一个用户感测多点触摸事件的多触摸面板，随后显示对应于所述多点触摸事件的指令结果; 耦合到所述处理器以将所述多个触摸面板划分为至少两个子显示区域的显示分割模块; 多用户操作模块被存储在存储介质中以指示显示分割模块执行多用户模式或单用户模式，从而允许多个用户同时在所述至少两个子显示区域上操纵虚拟对象。

    Source synchronized data transmission circuit
    9.
    发明授权
    Source synchronized data transmission circuit 失效
    源同步数据传输电路

    公开(公告)号：US5754835A

    公开(公告)日：1998-05-19

    申请号：US805287

    申请日：1997-02-25

    申请人： Allan Lin ,  Jay Deng

    发明人： Allan Lin ,  Jay Deng

    IPC分类号： H03L7/099 ,  H04L7/00 ,  H04L7/033 ,  H04L25/493 ,  H04L25/52 ,  G06F1/06

    CPC分类号： H04L7/0091 ,  H04L25/493 ,  H03L7/0995 ,  H04L7/0008

    摘要： A data source circuit and a complementary data recovery circuit which can transmit and receive data at a higher rate than a conventional data source circuit which uses similar fabrication technology. A data source circuit of the present invention has an input for receiving a periodic source clock signal having a period T; a synchronization signal generator for generating, based on said downstream-clock signal, a series of one or more periodic synchronization signals having periods substantially equal to T, each synchronization signal being delayed from a previous synchronization signal; and a transmitter for transmitting one or more sub-words of a multi-bit data word, each sub-word having one or more bits, separate ones of said one or more sub-words being transmitted responsive to separate progressively delayed combined pairs of said synchronization signals. In a preferred embodiment of the present invention particularly suited for use in a point to point (e.g. a ring-type) data network, a recovery circuit and a source circuit are integrated as a receiver/retransmission node.

    摘要翻译： 数据源电路和互补数据恢复电路，其能够以比使用类似制造技术的常规数据源电路更高的速率发送和接收数据。 本发明的数据源电路具有用于接收具有周期T的周期性源时钟信号的输入端; 同步信号发生器，用于基于所述下行时钟信号产生一系列具有基本上等于T的周期的周期性同步信号，每个同步信号从先前的同步信号延迟; 以及发送器，用于发送多比特数据字的一个或多个子字，每个子字具有一个或多个比特，所述一个或多个子字中的不同的子字响应于分离的逐渐延迟的所述组合对而被发送 同步信号 在本发明的一个优选实施例中，特别适用于点对点（例如环型）数据网络，恢复电路和源电路被集成为接收机/重传节点。

    Circuit for coupling an event indication signal across asynchronous time domains
    10.
    发明授权
    Circuit for coupling an event indication signal across asynchronous time domains 失效
    用于跨异步时域耦合事件指示信号的电路

    公开(公告)号：US5726595A

    公开(公告)日：1998-03-10

    申请号：US745270

    申请日：1996-11-08

    申请人： Allan Lin ,  L. Vincent Xie

    发明人： Allan Lin ,  L. Vincent Xie

    IPC分类号： G06F1/10 ,  H04L7/027 ,  H04L7/02

    CPC分类号： H04L7/027 ,  G06F1/10

    摘要： A circuit is for re-synchronizing an event indication signal received from a foreign domain to generate a result indication signal that is re-synchronized to a host clock signal. The event indication signal is received from the foreign domain at a first input terminal; and a host clock signal is received at a second input terminal. Edge-triggered flip flop circuitry of the circuit has a clock input, a data input, and a data output. The clock input is coupled to the second input terminal and the data input is coupled to receive a latch output signal. The edge-triggered flip flop circuitry clocks the latch output signal to the data output of the flip flop circuitry, to generate a result event indication signal, in response to a transition in the host clock signal. Delay circuitry is coupled to the first input terminal to receive the event indication signal. The delay circuitry provides a delayed event indication signal having a phase that is delayed from the event indication signal. Transparent latch circuitry latches the delayed event indication signal responsive to a latch control signal, and combination circuitry is coupled to receive the event indication signal and the result event indication signal, and provides a combination thereof as the latch control signal.

    摘要翻译： 电路用于重新同步从外部域接收到的事件指示信号，以产生与主机时钟信号重新同步的结果指示信号。 在第一输入端从外界接收事件指示信号; 并且在第二输入端接收主机时钟信号。 电路的边沿触发触发器电路具有时钟输入，数据输入和数据输出。 时钟输入耦合到第二输入端，并且数据输入被耦合以接收锁存输出信号。 边沿触发的触发器电路将锁存器输出信号时钟反馈到触发器电路的数据输出，以响应于主机时钟信号中的转换而产生结果事件指示信号。 延迟电路耦合到第一输入端以接收事件指示信号。 延迟电路提供具有从事件指示信号延迟的相位的延迟事件指示信号。 透明锁存电路响应锁存控制信号锁存延迟事件指示信号，并且组合电路被耦合以接收事件指示信号和结果事件指示信号，并提供其组合作为锁存控制信号。