发明申请
US20060101363A1 Method of associating timing violations with critical structures in an integrated circuit design
失效
将定时违规与集成电路设计中的关键结构相关联的方法
- 专利标题： Method of associating timing violations with critical structures in an integrated circuit design
- 专利标题（中）： 将定时违规与集成电路设计中的关键结构相关联的方法
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申请号： US10984115申请日： 2004-11-08
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公开(公告)号： US20060101363A1公开(公告)日： 2006-05-11
- 发明人: Randall Fry , Gregory Pierce , Juergen Lahner
- 申请人： Randall Fry , Gregory Pierce , Juergen Lahner
- 专利权人： LSI Logic Corporation
- 当前专利权人： LSI Logic Corporation
- 主分类号： G06F17/50
- IPC分类号： G06F17/50 ; G06F9/45
摘要：
A method and computer program product for associating timing violations with critical structures in an integrated circuit design include steps of: (a) receiving as input an integrated circuit design; (b) identifying a critical structure in the integrated circuit design; and (c) generating as output a script for a static timing analysis tool that includes a timing check for a path having a start point at an input of the critical structure and an end point at an output of the critical structure.
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