- 专利标题： Single-stage and multi-stage low power interconnect architectures
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申请号： US11314236申请日： 2005-12-22
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公开(公告)号： US20060109028A1公开(公告)日： 2006-05-25
- 发明人: Maged Ghoneima , Peter Caputa , Muhammad Khellah , Ram Krishnamurthy , James Tschanz , Yibin Ye , Vivek De , Yehia Ismail
- 申请人： Maged Ghoneima , Peter Caputa , Muhammad Khellah , Ram Krishnamurthy , James Tschanz , Yibin Ye , Vivek De , Yehia Ismail
- 专利权人： INTEL CORPORATION
- 当前专利权人： INTEL CORPORATION
- 主分类号： H03K19/173
- IPC分类号： H03K19/173
摘要：
An interconnect architecture is provided to reduce power consumption. A first driver may drive signals on a first interconnect and a second driver may drive signals on a second interconnect. The first driver may be powered by a first voltage and the second driver may be powered by a second voltage different than the first voltage.
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