公开(公告)号：US08769376B2

公开(公告)日：2014-07-01

申请号：US13626435

申请日：2012-09-25

Applicant: Muhammad Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Nam Sung Kim ,  Vivek De

Inventor： Muhammad Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Nam Sung Kim ,  Vivek De

IPC: G11C29/00

CPC classification number: G11C29/42 ,  G11C11/4125 ,  G11C11/417 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C29/12005 ,  G11C29/50 ,  G11C2029/0409 ,  G11C2029/0411 ,  G11C2029/5004

Abstract: Described herein is an apparatus for adjusting a power supply level for a memory cell to improve stability of a memory unit. The apparatus comprises memory circuitry including memory cells, error detection circuitry to detect error in data stored by memory cells of the memory circuitry, and supply voltage control circuitry to increase supply voltage for one or more memory cells of the memory circuitry based at least in part on detected error.

公开(公告)号：US20100146368A1

公开(公告)日：2010-06-10

申请号：US12331255

申请日：2008-12-09

Applicant: Zeshan A. Chishti ,  Alaa R. Alameldeen ,  Chris Wilkerson ,  Wei Wu ,  Dinesh Somasekhar ,  Muhammad Khellah ,  Shih-Lien Lu

Inventor： Zeshan A. Chishti ,  Alaa R. Alameldeen ,  Chris Wilkerson ,  Wei Wu ,  Dinesh Somasekhar ,  Muhammad Khellah ,  Shih-Lien Lu

IPC: H03M13/05 ,  G06F11/10

CPC classification number: H03M13/2921 ,  G06F11/1064 ,  H03M13/1102 ,  H03M13/13 ,  H03M13/15 ,  H03M13/1515 ,  H03M13/2906 ,  H03M13/2918

Abstract: A processor may comprise a cache, which may be divided into a first and second section while the processor operates in a low-power mode. A cache line of the first section may be fragmented into segments. A first encoder may generate first data bits and check bits while encoding a first portion of a data stream and a second encoder may, separately, generate second data bits and check bits while encoding a second portion of the data stream. The first data bits may be stored in a first segment of the first section and the check bits in a first portion of the second section that is associated with the first segment. The first decoder may correct errors in multiple bit positions within the first data bits using the check bits stored in the first portion and the second decoder may, separately, decode the second data bits using the second set of check bits.

Abstract translation: 处理器可以包括高速缓存，其可以在处理器以低功率模式操作时被分成第一和第二部分。 第一部分的高速缓存行可以被分段成段。 第一编码器可以在对数据流的第一部分进行编码的同时产生第一数据位和校验位，并且第二编码器可以分别在编码数据流的第二部分时生成第二数据位和校验位。 第一数据位可以存储在第一部分的第一部分中，并且与第一部分相关联的第二部分的第一部分中的校验位。 第一解码器可以使用存储在第一部分中的校验位来校正第一数据位中的多位位置中的错误，并且第二解码器可以单独地使用第二组校验位对第二数据位进行解码。

公开(公告)号：US20070076463A1

公开(公告)日：2007-04-05

申请号：US11239903

申请日：2005-09-30

Applicant: Ali Keshavarzi ,  Fabrice Paillet ,  Muhammad Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen Tang ,  Mohsen Alavi ,  Vivek De

Inventor： Ali Keshavarzi ,  Fabrice Paillet ,  Muhammad Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen Tang ,  Mohsen Alavi ,  Vivek De

IPC: G11C17/00

CPC classification number: G11C17/16 ,  G11C17/146 ,  G11C17/165 ,  G11C29/027

Abstract: According to embodiments of the present invention, a one-time programmable (OTP) cell includes an access transistor coupled to an antifuse transistor. In on embodiment, access transistor has a gate oxide thickness that is greater than the gate oxide thickness of the antifuse transistor so that if the antifuse transistor is programmed, the voltage felt across the gate/drain junction of the access transistor is insufficient to cause the gate oxide of the access transistor to break down. The dual gate oxide OTP cell may be used in an array in which only one OTP cell is programmed at a time. The dual gate oxide OTP cell also may be used in an array in which several OTP cells are programmed simultaneously.

Abstract translation: 根据本发明的实施例，一次可编程（OTP）单元包括耦合到反熔丝晶体管的存取晶体管。 在实施例中，存取晶体管具有大于反熔丝晶体管的栅极氧化物厚度的栅极氧化物厚度，使得如果对反熔丝晶体管进行编程，则跨越存取晶体管的栅极/漏极结的电压不足以导致 栅极氧化层的存取晶体管分解。 双栅氧化物OTP单元可以用于其中一次只编写一个OTP单元的阵列中。 双栅氧化物OTP电池也可用于其中同时编程几个OTP电池的阵列中。

公开(公告)号：US20060291265A1

公开(公告)日：2006-12-28

申请号：US11169106

申请日：2005-06-27

Applicant: Gerhard Schrom ,  Fabrice Paillet ,  Tanay Karnik ,  Dinesh Somasekhar ,  Yibin Ye ,  Ali Keshavarzi ,  Muhammad Khellah ,  Vivek De

Inventor： Gerhard Schrom ,  Fabrice Paillet ,  Tanay Karnik ,  Dinesh Somasekhar ,  Yibin Ye ,  Ali Keshavarzi ,  Muhammad Khellah ,  Vivek De

IPC: G11C17/00

CPC classification number: G11C17/18

Abstract: A system includes a pull-up circuit to program a memory cell. The pull-up circuit may include a level shifter to receive a control signal, a supply voltage, and one or more of a plurality of rail voltages, each of the plurality of rail voltages substantially equal to a respective integer multiple of the supply voltage, and to generate a second control signal, and a cascode stage. The cascode stage may include a plurality of transistors, a gate voltage of each of the plurality of transistors to be controlled at least in part by a respective one of the second control signal, the supply voltage, and at least one of the plurality of rail voltages, and an output node to provide a cell programming signal.

Abstract translation: 系统包括用于对存储器单元进行编程的上拉电路。 上拉电路可以包括电平移位器以接收控制信号，电源电压以及多个轨道电压中的一个或多个，多个轨道电压中的每一个基本上等于电源电压的相应整数倍， 并产生第二控制信号和共源共栅级。 共源共栅级可以包括多个晶体管，多个晶体管中的每一个的栅极电压至少部分地由第二控制信号，电源电压和多个轨道中的至少一个轨道 电压和输出节点以提供单元编程信号。

公开(公告)号：US20060268626A1

公开(公告)日：2006-11-30

申请号：US11137905

申请日：2005-05-25

Applicant: Fatih Hamzaoglu ,  Kevin Zhang ,  Nam Kim ,  Muhammad Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Vivek De ,  Bo Zheng

Inventor： Fatih Hamzaoglu ,  Kevin Zhang ,  Nam Kim ,  Muhammad Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Vivek De ,  Bo Zheng

IPC: G11C7/10

CPC classification number: G11C5/14 ,  G11C11/413

Abstract: In some embodiments, a memory array is provided with cells that when written to or read from, can have modified supplies to enhance their read stability and/or write margin performance. Other embodiments may be disclosed and/or claimed.

Abstract translation: 在一些实施例中，存储器阵列具有当写入或读取时可以具有修改的电源以增强其读取稳定性和/或写入裕度性能的单元。 可以公开和/或要求保护其他实施例。

公开(公告)号：US20060104128A1

公开(公告)日：2006-05-18

申请号：US11320789

申请日：2005-12-30

Applicant: Dinesh Somasekhar ,  Muhammad Khellah ,  Yibin Ye ,  Vivek De ,  James Tschanz ,  Stephen Tang

Inventor： Dinesh Somasekhar ,  Muhammad Khellah ,  Yibin Ye ,  Vivek De ,  James Tschanz ,  Stephen Tang

IPC: G11C7/10

CPC classification number: G11C5/143 ,  G11C5/147 ,  G11C11/413

Abstract: An apparatus and method are provided for limiting a drop of a supply voltage in an SRAM device to retain the state of the memory during an IDLE state. The apparatus may include a memory array, a sleep device, and a clamping circuit. The clamping circuit may be configured to activate the sleep device when a voltage drop across the memory array falls below a preset voltage and the memory array is in an IDLE state.

公开(公告)号：US07031203B2

公开(公告)日：2006-04-18

申请号：US11066395

申请日：2005-02-28

Applicant: Stephen Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Vivek De

Inventor： Stephen Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Vivek De

IPC: G11C5/14

CPC classification number: H01L27/108 ,  G11C11/404 ,  G11C11/4085 ,  H01L29/7841

Abstract: A DRAM memory cell uses a single transistor to perform the data storage and switching functions of a conventional cell. The transistor has a floating channel body which stores a potential that corresponds to one of two digital data values. The transistor further includes a gate connected to a first word line, a drain connected to a second word line, and a source connected to a bit line. By setting the word and bit lines to specific voltage states, the channel body stores a digital one potential as a result of impact ionization and a digital zero value as a result of forward bias of body-to-source junction.

Abstract translation: DRAM存储单元使用单个晶体管来执行常规单元的数据存储和切换功能。 晶体管具有浮置通道体，其存储对应于两个数字数据值之一的电位。 晶体管还包括连接到第一字线的栅极，连接到第二字线的漏极和连接到位线的源极。 通过将单词和位线设置为特定的电压状态，通道体由于碰撞电离而存储数字一个电位，并且由于体对源结的正向偏置而存储数字零值。

公开(公告)号：US20060071646A1

公开(公告)日：2006-04-06

申请号：US10956285

申请日：2004-09-30

Applicant: Fabrice Paillet ,  Ali Keshavarzi ,  Muhammad Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen Tang ,  Alavi Mohsen ,  Vivek De

Inventor： Fabrice Paillet ,  Ali Keshavarzi ,  Muhammad Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen Tang ,  Alavi Mohsen ,  Vivek De

IPC: H02J7/00

CPC classification number: G11C17/16 ,  G11C17/18

Abstract: A method is described that induced dielectric breakdown within a capacitor's dielectric material while driving a current through the capacitor. The current is specific to data that is being written into the capacitor. The method also involves reading the data by interpreting behavior of the capacitor that is determined by the capacitor's resistance, where, the capacitor's resistance is a consequence of the inducing and the driving.

Abstract translation: 描述了一种在驱动电流通过电容器的同时在电容器的电介质材料内感应电介质击穿的方法。 电流特定于正在写入电容器的数据。 该方法还涉及通过解释由电容器电阻确定的电容器的行为来读取数据，其中电容器的电阻是诱导和驱动的结果。

公开(公告)号：US20060067126A1

公开(公告)日：2006-03-30

申请号：US10954931

申请日：2004-09-30

Applicant: Stephen Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Shih-Lien Lu ,  Vivek De

Inventor： Stephen Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Shih-Lien Lu ,  Vivek De

IPC: G11C16/04 ,  G11C11/34

CPC classification number: G11C16/12 ,  G11C11/4076 ,  G11C2216/14

Abstract: A system to write to a plurality of memory cells coupled to a word line, each of the plurality of memory cells comprising a transistor having a source, a drain, a body and a gate coupled to the word line. Some embodiments provide biasing of one or more of the plurality of memory cells in saturation to inject charge carriers into the body of the one or more of the plurality of memory cells, and biasing of each of the plurality of memory cells in accumulation to tunnel charge carriers from the body of each of the plurality of memory cells to the gate of each of the plurality of memory cells.

公开(公告)号：US20060054971A1

公开(公告)日：2006-03-16

申请号：US11268430

申请日：2005-11-07

Applicant: Ali Keshavarzi ,  Stephen Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Shih-Lien Lu ,  Vivek De

Inventor： Ali Keshavarzi ,  Stephen Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Shih-Lien Lu ,  Vivek De

IPC: H01L29/76

CPC classification number: G11C11/404 ,  G11C2211/4016 ,  H01L27/0207 ,  H01L27/0214 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/108

Abstract: Some embodiments provide a memory cell comprising a body region doped with charge carriers of a first type, a source region disposed in the body region and doped with charge carriers of a second type, and a drain region disposed in the body region and doped with charge carriers of the second type. According to some embodiments, the body region, the source region, and the drain region are oriented in a first direction, the body region and the source region form a first junction, and the body region and the drain region form a second junction. Moreover, a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased. Some embodiments further include a transistor oriented in a second direction, wherein the second direction is not parallel to the first direction.

Abstract translation: 一些实施例提供一种存储单元，其包括掺杂有第一类型的电荷载体的体区，设置在体区中的源极区，并掺杂有第二类型的电荷载流子，以及设置在体区中的掺杂电荷 第二种载体。 根据一些实施例，身体区域，源区域和漏极区域在第一方向上定向，身体区域和源区域形成第一结，并且体区域和漏区域形成第二结。 此外，在第一结无偏置的情况下，从体区到源极区的第一结的导电率基本上小于从体区到漏区的第二结的导电率，在第二结 是不偏不倚的 一些实施例还包括在第二方向上取向的晶体管，其中第二方向不平行于第一方向。