Invention Application
- Patent Title: MOS transistor with elevated source/drain structure
- Patent Title (中): 具有升高的源极/漏极结构的MOS晶体管
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Application No.: US11388868Application Date: 2006-03-24
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Publication No.: US20060163558A1Publication Date: 2006-07-27
- Inventor: Seung-hwan Lee , Moon-han Park , Hwa-sung Rhee , Ho Lee , Jae-yoon Yoo
- Applicant: Seung-hwan Lee , Moon-han Park , Hwa-sung Rhee , Ho Lee , Jae-yoon Yoo
- Assignee: Samsung Electronics, Co., Ltd.
- Current Assignee: Samsung Electronics, Co., Ltd.
- Priority: KR03-30614 20030514
- Main IPC: H01L31/109
- IPC: H01L31/109

Abstract:
In a metal-oxide semiconductor (MOS) transistor with an elevated source/drain structure and in a method of fabricating the MOS transistor with the elevated source/drain structure using a selective epitaxy growth (SEG) process, a source/drain extension junction is formed after an epi-layer is formed, thereby preventing degradation of the source/drain junction region. In addition, the source/drain extension junction is partially overlapped by a lower portion of the gate layer, since two gate spacers are formed and two elevated source/drain layers are formed in accordance with the SEG process. This mitigates the short channel effect and reduces sheet resistance in the source/drain layers and the gate layer.
Public/Granted literature
- US07368792B2 MOS transistor with elevated source/drain structure Public/Granted day:2008-05-06
Information query
IPC分类: