公开(公告)号：US20060163558A1

公开(公告)日：2006-07-27

申请号：US11388868

申请日：2006-03-24

申请人： Seung-hwan Lee ,  Moon-han Park ,  Hwa-sung Rhee ,  Ho Lee ,  Jae-yoon Yoo

发明人： Seung-hwan Lee ,  Moon-han Park ,  Hwa-sung Rhee ,  Ho Lee ,  Jae-yoon Yoo

IPC分类号： H01L31/109

CPC分类号： H01L29/7834 ,  H01L29/42376 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628

摘要： In a metal-oxide semiconductor (MOS) transistor with an elevated source/drain structure and in a method of fabricating the MOS transistor with the elevated source/drain structure using a selective epitaxy growth (SEG) process, a source/drain extension junction is formed after an epi-layer is formed, thereby preventing degradation of the source/drain junction region. In addition, the source/drain extension junction is partially overlapped by a lower portion of the gate layer, since two gate spacers are formed and two elevated source/drain layers are formed in accordance with the SEG process. This mitigates the short channel effect and reduces sheet resistance in the source/drain layers and the gate layer.

摘要翻译： 在具有升高的源极/漏极结构的金属氧化物半导体（MOS）晶体管中，并且使用选择性外延生长（SEG）工艺制造具有升高的源极/漏极结构的MOS晶体管的方法中，源极/漏极延伸结是 在形成外延层之后形成，从而防止源极/漏极结区域的劣化。 此外，源极/漏极延伸结部分由栅极层的下部部分地重叠，因为形成了两个栅极间隔物，并且根据SEG工艺形成两个升高的源极/漏极层。 这减轻了短沟道效应并降低了源极/漏极层和栅极层中的薄层电阻。

公开(公告)号：US07368792B2

公开(公告)日：2008-05-06

申请号：US11388868

申请日：2006-03-24

申请人： Seung-hwan Lee ,  Moon-han Park ,  Hwa-sung Rhee ,  Ho Lee ,  Jae-yoon Yoo

发明人： Seung-hwan Lee ,  Moon-han Park ,  Hwa-sung Rhee ,  Ho Lee ,  Jae-yoon Yoo

IPC分类号： H01L29/76

CPC分类号： H01L29/7834 ,  H01L29/42376 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628

摘要： In a metal-oxide semiconductor (MOS) transistor with an elevated source/drain structure and in a method of fabricating the MOS transistor with the elevated source/drain structure using a selective epitaxy growth (SEG) process, a source/drain extension junction is formed after an epi-layer is formed, thereby preventing degradation of the source/drain junction region. In addition, the source/drain extension junction is partially overlapped by a lower portion of the gate layer, since two gate spacers are formed and two elevated source/drain layers are formed in accordance with the SEG process. This mitigates the short channel effect and reduces sheet resistance in the source/drain layers and the gate layer.

摘要翻译： 在具有升高的源极/漏极结构的金属氧化物半导体（MOS）晶体管中，并且使用选择性外延生长（SEG）工艺制造具有升高的源极/漏极结构的MOS晶体管的方法中，源极/漏极延伸结是 在形成外延层之后形成，从而防止源极/漏极结区域的劣化。 此外，源极/漏极延伸结部分由栅极层的下部部分地重叠，因为形成了两个栅极间隔物，并且根据SEG工艺形成两个升高的源极/漏极层。 这减轻了短沟道效应并降低了源极/漏极层和栅极层中的薄层电阻。

公开(公告)号：US07033895B2

公开(公告)日：2006-04-25

申请号：US10823420

申请日：2004-04-13

申请人： Seung-hwan Lee ,  Moon-han Park ,  Hwa-sung Rhee ,  Ho Lee ,  Jae-yoon Yoo

发明人： Seung-hwan Lee ,  Moon-han Park ,  Hwa-sung Rhee ,  Ho Lee ,  Jae-yoon Yoo

IPC分类号： H01L21/336

CPC分类号： H01L29/7834 ,  H01L29/42376 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628

摘要： In a metal-oxide semiconductor (MOS) transistor with an elevated source/drain structure and in a method of fabricating the MOS transistor with the elevated source/drain structure using a selective epitaxy growth (SEG) process, a source/drain extension junction is formed after an epi-layer is formed, thereby preventing degradation of the source/drain junction region. In addition, the source/drain extension junction is partially overlapped by a lower portion of the gate layer, since two gate spacers are formed and two elevated source/drain layers are formed in accordance with the SEG process. This mitigates the short channel effect and reduces sheet resistance in the source/drain layers and the gate layer.

摘要翻译： 在具有升高的源极/漏极结构的金属氧化物半导体（MOS）晶体管中，并且使用选择性外延生长（SEG）工艺制造具有升高的源极/漏极结构的MOS晶体管的方法中，源极/漏极延伸结是 在形成外延层之后形成，从而防止源极/漏极结区域的劣化。 此外，源极/漏极延伸结部分由栅极层的下部部分地重叠，因为形成了两个栅极间隔物，并且根据SEG工艺形成两个升高的源极/漏极层。 这减轻了短沟道效应并降低了源极/漏极层和栅极层中的薄层电阻。

公开(公告)号：US07084041B2

公开(公告)日：2006-08-01

申请号：US10795175

申请日：2004-03-05

申请人： Hwa-sung Rhee ,  Jae-yoon Yoo ,  Ho Lee ,  Seung-hwan Lee ,  Byou-ree Lim

发明人： Hwa-sung Rhee ,  Jae-yoon Yoo ,  Ho Lee ,  Seung-hwan Lee ,  Byou-ree Lim

IPC分类号： H01L21/331

CPC分类号： H01L29/66287 ,  H01L29/0804 ,  H01L29/7375 ,  H01L29/7378

摘要： A method of manufacturing a bipolar device including pre-treatment using germane gas and a bipolar device manufactured by the same. The method includes forming a single crystalline silicon layer for a base region on a collector region; and forming a polysilicon layer for an emitter region thereon. Here, before the polysilicon layer is formed, the single crystalline silicon layer is pre-treated using germane gas. Thus, an oxide layer is removed from the single crystalline silicon layer, and a germanium layer is formed on the single crystalline silicon layer, thus preventing Si-rearrangement.

摘要翻译： 一种制造双极器件的方法，其包括使用锗烷气体的预处理和由其制造的双极器件。 该方法包括在集电区上形成用于基区的单晶硅层; 并在其上形成发射极区的多晶硅层。 这里，在形成多晶硅层之前，使用锗烷气预处理单晶硅层。 因此，从单晶硅层去除氧化物层，并且在单晶硅层上形成锗层，从而防止Si重排。

公开(公告)号：US20090020845A1

公开(公告)日：2009-01-22

申请号：US12106671

申请日：2008-04-21

申请人： Dong-suk Shin ,  Moon-han Park ,  Joo-won Lee ,  Jae-yoon Yoo ,  Tae-gyun Kim

发明人： Dong-suk Shin ,  Moon-han Park ,  Joo-won Lee ,  Jae-yoon Yoo ,  Tae-gyun Kim

IPC分类号： H01L21/762 ,  H01L23/00

CPC分类号： H01L21/3105 ,  H01L21/31155 ,  H01L21/76232

摘要： A semiconductor device includes a substrate having a trench, a sidewall liner that covers inner walls of the trench, a doped oxide film liner on the sidewall liner in the trench, and a gap-fill insulating film that buries the trench on the doped oxide film liner. In order to form the doped oxide film liner, an oxide film liner is doped with a dopant under a plasma atmosphere. Related methods are also disclosed.

摘要翻译： 半导体器件包括具有沟槽的衬底，覆盖沟槽的内壁的侧壁衬套，沟槽中的侧壁衬里上的掺杂氧化膜衬垫，以及将掺杂氧化物膜上的沟槽埋入的间隙填充绝缘膜 衬垫。 为了形成掺杂的氧化物膜衬垫，在等离子体气氛下，掺杂有氧化物膜衬垫。 还公开了相关方法。

公开(公告)号：US20060183296A1

公开(公告)日：2006-08-17

申请号：US11398536

申请日：2006-04-06

申请人： Jae-yoon Yoo ,  Moon-han Park ,  Dong-ho Ahn ,  Sug-hun Hong ,  Kyung-won Park ,  Jeong-soo Lee

发明人： Jae-yoon Yoo ,  Moon-han Park ,  Dong-ho Ahn ,  Sug-hun Hong ,  Kyung-won Park ,  Jeong-soo Lee

IPC分类号： H01L21/76

CPC分类号： H01L21/76232

摘要： An isolation method for a semiconductor device where an insulating mask layer is formed on desired regions of a semiconductor substrate. A trench is formed to a desired depth in the semiconductor substrate using the insulating mask layer as a mask. An oxide layer is formed on the insulating mask layer and on the sidewall of the trench. A trench liner layer is formed on the oxide layer. An insulating filler layer is formed in the trench in the semiconductor substrate, on which the trench liner layer is formed, so as to fill the trench. The insulating mask layer is removed. According to the isolation method for a semiconductor device, it is possible to reduce dents from occurring along the edge of the trench, reduce a bird's beak type oxide layer from occurring at an interface between the insulating mask layers, decrease the leakage current, or improve the electrical characteristics, such as threshold voltage.

公开(公告)号：US06835621B2

公开(公告)日：2004-12-28

申请号：US10455676

申请日：2003-06-05

申请人： Jae-yoon Yoo ,  Moon-han Park ,  Dae-jin Kwon

发明人： Jae-yoon Yoo ,  Moon-han Park ,  Dae-jin Kwon

IPC分类号： H01L218247

CPC分类号： H01L27/11568 ,  H01L21/022 ,  H01L21/02238 ,  H01L21/02326 ,  H01L21/28282 ,  H01L21/3144 ,  H01L21/31612 ,  H01L21/32105 ,  H01L27/115 ,  H01L29/66833

摘要： In a method of fabricating a non-volatile memory device with a silicon-oxide-nitride-oxide-silicon (SONOS) structure, a silicon nitride layer, which is a charge trapping layer, and a polysilicon layer, which is a control gate electrode, are electrically isolated from one another in the resulting structure. According to the method, a silicon oxide layer as a tunneling layer and a silicon nitride layer pattern as a charge trapping layer are formed on a semiconductor substrate; an oxidation process is performed to form a silicon nitride oxide layer, as a blocking layer, at top and sides of the silicon nitride layer pattern and to form a gate insulating layer at an exposed portion of the semiconductor substrate; and a control gate electrode is formed on the silicon nitride oxide layer and the gate insulating layer.

摘要翻译： 在制造具有氧化硅 - 氮化物 - 氧化物 - 硅（SONOS）结构的非易失性存储器件的方法中，作为电荷俘获层的氮化硅层和作为控制栅电极的多晶硅层 在所得结构中彼此电隔离。 根据该方法，在半导体衬底上形成作为隧穿层的氧化硅层和作为电荷俘获层的氮化硅层图案; 进行氧化处理以在氮化硅层图案的顶部和侧面形成氮化硅氧化物层作为阻挡层，并在半导体衬底的暴露部分形成栅极绝缘层; 并且在氮氧化硅层和栅极绝缘层上形成控制栅电极。

公开(公告)号：US07618868B2

公开(公告)日：2009-11-17

申请号：US11381481

申请日：2006-05-03

申请人： Jae-yoon Yoo ,  Young-gun Ko

发明人： Jae-yoon Yoo ,  Young-gun Ko

IPC分类号： H01L21/336

CPC分类号： H01L21/823468 ,  H01L21/823864 ,  H01L27/088 ,  H01L27/092

摘要： Provided are a more stable semiconductor integrated circuit device and a method of manufacturing the same. The method includes providing a semiconductor substrate comprising a first transistor region having a stacked structure of a first gate insulating layer and a first gate and a second transistor region having a stacked structure of a second gate insulating layer and a second gate, forming a blocking layer in the first transistor region, conformally forming a second oxide layer on lateral surfaces of the second gate insulating layer and the second gate and on an exposed surface of the semiconductor substrate by performing oxidation in the second transistor region, removing the blocking layer of the first transistor region, forming a pre-spacer layer on the entire surface of the semiconductor substrate, forming a first spacer by anisotropically etching the pre-spacer layer of the first transistor region and forming a second spacer by anisotropically etching the second oxide layer and the pre-spacer layer of the second transistor region, and forming source/drain regions in the semiconductor substrate to complete a first transistor and a second transistor.

摘要翻译： 提供了一种更稳定的半导体集成电路器件及其制造方法。 该方法包括提供一种半导体衬底，其包括具有第一栅极绝缘层和第一栅极的堆叠结构的第一晶体管区域和具有第二栅极绝缘层和第二栅极的堆叠结构的第二晶体管区域，形成阻挡层 在第一晶体管区域中，通过在第二晶体管区域中进行氧化，在第二栅极绝缘层和第二栅极的侧表面上和半导体衬底的暴露表面上保形地形成第二氧化物层，去除第一 晶体管区域，在半导体衬底的整个表面上形成预分隔层，通过各向异性蚀刻第一晶体管区域的预隔离层形成第一间隔物，并通过各向异性蚀刻第二氧化物层和预先形成第二间隔层，形成第二间隔物 - 第二晶体管区域的间隔层，以及在半导体中形成源极/漏极区域 r衬底以完成第一晶体管和第二晶体管。

公开(公告)号：US06486039B2

公开(公告)日：2002-11-26

申请号：US09933039

申请日：2001-08-21

申请人： Jae-yoon Yoo ,  Jeong-soo Lee ,  Nae-in Lee

发明人： Jae-yoon Yoo ,  Jeong-soo Lee ,  Nae-in Lee

IPC分类号： H01L21302

CPC分类号： H01L21/76229 ,  H01L21/76237

摘要： A method of fabricating a trench isolation structure in a high-density semiconductor device that provides an isolation characteristic that is independent of the properties of adjacent MOS transistor devices, wherein a first trench in a first isolation area and a second trench implanted are formed on a semiconductor substrate, a nitrogen (N)-rich silicon layer is formed on the sidewall in a second isolation area, a subsequent oxidation process may be employed to fabricate oxide layers, each having a different thickness, on the sidewall surfaces of the first and second trenches. When the first and second oxide-layered trenches are filled with a stress relief liner and a dielectric material, the different thicknesses of the oxides prevent leakage currents from flowing to an adjacent semiconductor device, regardless of the doping properties of each device.

公开(公告)号：US06383877B1

公开(公告)日：2002-05-07

申请号：US09573268

申请日：2000-05-18

申请人： Dong-ho Ahn ,  Ja-hum Ku ,  Chul-sung Kim ,  Jae-yoon Yoo ,  Sug-hun Hong ,  Chul-joon Choi

发明人： Dong-ho Ahn ,  Ja-hum Ku ,  Chul-sung Kim ,  Jae-yoon Yoo ,  Sug-hun Hong ,  Chul-joon Choi

IPC分类号： H01L21425

CPC分类号： H01L29/66598 ,  H01L21/28518 ,  H01L21/76232 ,  H01L21/823481 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66636

摘要： A method of forming a T-shaped isolation layer, a method of forming an elevated salicide source/drain region using the same, and a semiconductor device having the T-shaped isolation layer are provided. In the method of forming the T-shaped isolation layer, an isolation layer having a narrow trench region in the lower portion thereof and a wide trench region in the upper portion thereof is formed on a semiconductor substrate. Also, in the method of forming the elevated salicide source/drain region, the method of forming the T-shaped isolation layer is used. In particular, conductive impurities can also be implanted into the lower portion of the wide trench region which constitutes the head of the T-shaped isolation layer and is extended to both sides from the upper end of the narrow trench region by controlling the depth of the wide trench region in an ion implantation step for forming the source/drain region.

摘要翻译： 提供形成T形隔离层的方法，使用该方法形成提高的自对准硅化物源极/漏极区域的方法以及具有T形隔离层的半导体器件。 在形成T形隔离层的方法中，在半导体衬底上形成在其下部具有窄沟槽区和其上部宽沟槽区的隔离层。 此外，在形成升高的自对准硅化物源极/漏极区域的方法中，使用形成T形隔离层的方法。 特别地，也可以将导电杂质注入构成T形隔离层的头部的宽沟槽区域的下部，并且通过控制该窄沟槽区域的深度而从窄沟槽区域的上端延伸到两侧 在用于形成源极/漏极区域的离子注入步骤中形成宽沟槽区域。