公开(公告)号：US07368792B2

公开(公告)日：2008-05-06

申请号：US11388868

申请日：2006-03-24

申请人： Seung-hwan Lee ,  Moon-han Park ,  Hwa-sung Rhee ,  Ho Lee ,  Jae-yoon Yoo

发明人： Seung-hwan Lee ,  Moon-han Park ,  Hwa-sung Rhee ,  Ho Lee ,  Jae-yoon Yoo

IPC分类号： H01L29/76

CPC分类号： H01L29/7834 ,  H01L29/42376 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628

摘要： In a metal-oxide semiconductor (MOS) transistor with an elevated source/drain structure and in a method of fabricating the MOS transistor with the elevated source/drain structure using a selective epitaxy growth (SEG) process, a source/drain extension junction is formed after an epi-layer is formed, thereby preventing degradation of the source/drain junction region. In addition, the source/drain extension junction is partially overlapped by a lower portion of the gate layer, since two gate spacers are formed and two elevated source/drain layers are formed in accordance with the SEG process. This mitigates the short channel effect and reduces sheet resistance in the source/drain layers and the gate layer.

摘要翻译： 在具有升高的源极/漏极结构的金属氧化物半导体（MOS）晶体管中，并且使用选择性外延生长（SEG）工艺制造具有升高的源极/漏极结构的MOS晶体管的方法中，源极/漏极延伸结是 在形成外延层之后形成，从而防止源极/漏极结区域的劣化。 此外，源极/漏极延伸结部分由栅极层的下部部分地重叠，因为形成了两个栅极间隔物，并且根据SEG工艺形成两个升高的源极/漏极层。 这减轻了短沟道效应并降低了源极/漏极层和栅极层中的薄层电阻。

公开(公告)号：US07033895B2

公开(公告)日：2006-04-25

申请号：US10823420

申请日：2004-04-13

申请人： Seung-hwan Lee ,  Moon-han Park ,  Hwa-sung Rhee ,  Ho Lee ,  Jae-yoon Yoo

发明人： Seung-hwan Lee ,  Moon-han Park ,  Hwa-sung Rhee ,  Ho Lee ,  Jae-yoon Yoo

IPC分类号： H01L21/336

CPC分类号： H01L29/7834 ,  H01L29/42376 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628

摘要： In a metal-oxide semiconductor (MOS) transistor with an elevated source/drain structure and in a method of fabricating the MOS transistor with the elevated source/drain structure using a selective epitaxy growth (SEG) process, a source/drain extension junction is formed after an epi-layer is formed, thereby preventing degradation of the source/drain junction region. In addition, the source/drain extension junction is partially overlapped by a lower portion of the gate layer, since two gate spacers are formed and two elevated source/drain layers are formed in accordance with the SEG process. This mitigates the short channel effect and reduces sheet resistance in the source/drain layers and the gate layer.

摘要翻译： 在具有升高的源极/漏极结构的金属氧化物半导体（MOS）晶体管中，并且使用选择性外延生长（SEG）工艺制造具有升高的源极/漏极结构的MOS晶体管的方法中，源极/漏极延伸结是 在形成外延层之后形成，从而防止源极/漏极结区域的劣化。 此外，源极/漏极延伸结部分由栅极层的下部部分地重叠，因为形成了两个栅极间隔物，并且根据SEG工艺形成两个升高的源极/漏极层。 这减轻了短沟道效应并降低了源极/漏极层和栅极层中的薄层电阻。

公开(公告)号：US20060163558A1

公开(公告)日：2006-07-27

申请号：US11388868

申请日：2006-03-24

申请人： Seung-hwan Lee ,  Moon-han Park ,  Hwa-sung Rhee ,  Ho Lee ,  Jae-yoon Yoo

发明人： Seung-hwan Lee ,  Moon-han Park ,  Hwa-sung Rhee ,  Ho Lee ,  Jae-yoon Yoo

IPC分类号： H01L31/109

CPC分类号： H01L29/7834 ,  H01L29/42376 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628

摘要： In a metal-oxide semiconductor (MOS) transistor with an elevated source/drain structure and in a method of fabricating the MOS transistor with the elevated source/drain structure using a selective epitaxy growth (SEG) process, a source/drain extension junction is formed after an epi-layer is formed, thereby preventing degradation of the source/drain junction region. In addition, the source/drain extension junction is partially overlapped by a lower portion of the gate layer, since two gate spacers are formed and two elevated source/drain layers are formed in accordance with the SEG process. This mitigates the short channel effect and reduces sheet resistance in the source/drain layers and the gate layer.

摘要翻译： 在具有升高的源极/漏极结构的金属氧化物半导体（MOS）晶体管中，并且使用选择性外延生长（SEG）工艺制造具有升高的源极/漏极结构的MOS晶体管的方法中，源极/漏极延伸结是 在形成外延层之后形成，从而防止源极/漏极结区域的劣化。 此外，源极/漏极延伸结部分由栅极层的下部部分地重叠，因为形成了两个栅极间隔物，并且根据SEG工艺形成两个升高的源极/漏极层。 这减轻了短沟道效应并降低了源极/漏极层和栅极层中的薄层电阻。

公开(公告)号：US07084041B2

公开(公告)日：2006-08-01

申请号：US10795175

申请日：2004-03-05

申请人： Hwa-sung Rhee ,  Jae-yoon Yoo ,  Ho Lee ,  Seung-hwan Lee ,  Byou-ree Lim

发明人： Hwa-sung Rhee ,  Jae-yoon Yoo ,  Ho Lee ,  Seung-hwan Lee ,  Byou-ree Lim

IPC分类号： H01L21/331

CPC分类号： H01L29/66287 ,  H01L29/0804 ,  H01L29/7375 ,  H01L29/7378

摘要： A method of manufacturing a bipolar device including pre-treatment using germane gas and a bipolar device manufactured by the same. The method includes forming a single crystalline silicon layer for a base region on a collector region; and forming a polysilicon layer for an emitter region thereon. Here, before the polysilicon layer is formed, the single crystalline silicon layer is pre-treated using germane gas. Thus, an oxide layer is removed from the single crystalline silicon layer, and a germanium layer is formed on the single crystalline silicon layer, thus preventing Si-rearrangement.

摘要翻译： 一种制造双极器件的方法，其包括使用锗烷气体的预处理和由其制造的双极器件。 该方法包括在集电区上形成用于基区的单晶硅层; 并在其上形成发射极区的多晶硅层。 这里，在形成多晶硅层之前，使用锗烷气预处理单晶硅层。 因此，从单晶硅层去除氧化物层，并且在单晶硅层上形成锗层，从而防止Si重排。

公开(公告)号：US20100233864A1

公开(公告)日：2010-09-16

申请号：US12656842

申请日：2010-02-17

申请人： Ho Lee ,  Moon-han Park ,  Hwa-sung Rhee ,  Myung-sun Kim ,  Hoi-sung Chung

发明人： Ho Lee ,  Moon-han Park ,  Hwa-sung Rhee ,  Myung-sun Kim ,  Hoi-sung Chung

IPC分类号： H01L21/336

CPC分类号： H01L29/4983 ,  H01L21/2236 ,  H01L21/265 ,  H01L21/76825 ,  H01L21/76829 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： Methods of fabricating a semiconductor device are provided, the methods include forming a gate stack on a substrate, forming an insulation layer on the substrate to cover the gate stack, forming a spacer at both side walls of the gate stack by etching the insulation layer, and ion implanting impurities in the spacer or the insulation layer.

摘要翻译： 提供了制造半导体器件的方法，所述方法包括在衬底上形成栅极堆叠，在衬底上形成绝缘层以覆盖栅极堆叠，通过蚀刻绝缘层在栅极堆叠的两个侧壁处形成间隔物， 以及在间隔物或绝缘层中离子注入杂质。

公开(公告)号：US20080135879A1

公开(公告)日：2008-06-12

申请号：US12029884

申请日：2008-02-12

申请人： Dong-suk Shin ,  Hwa-sung Rhee ,  Ueno Tetsuji ,  Ho Lee ,  Seung-hwan Lee

发明人： Dong-suk Shin ,  Hwa-sung Rhee ,  Ueno Tetsuji ,  Ho Lee ,  Seung-hwan Lee

IPC分类号： H01L27/092

CPC分类号： H01L29/66636 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/165 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/7848

摘要： In a method of fabricating a CMOS transistor, and a CMOS transistor fabricated according to the method, the characteristics of first and second conductivity type MOS transistors are both simultaneously improved. At the same time, the fabrication process is simplified by reducing the number of masks required. The method includes amorphizing the active region of only the second conductivity type MOS transistor, and performing selective etching to form a first recessed region of a first depth in the active region of the first conductivity type MOS transistor and a second recessed region of a second depth that is greater than the first depth in the active region of the second conductivity type MOS transistor. Selective epitaxial growth is performed in the first and second recessed regions to form an elevated epitaxial layer that fills the first recessed region and extends to a level that is above the upper surface of the semiconductor substrate and to form a recessed epitaxial layer that fills the second recessed region.

摘要翻译： 在制造CMOS晶体管的方法和根据该方法制造的CMOS晶体管的情况下，第一和第二导电型MOS晶体管的特性都同时改善。 同时，通过减少所需掩模的数量来简化制造过程。 该方法包括仅使第二导电型MOS晶体管的有源区非晶化，并进行选择性蚀刻，以在第一导电类型MOS晶体管的有源区中形成第一深度的第一凹陷区域和第二深度的第二凹陷区域 大于第二导电型MOS晶体管的有源区中的第一深度。 在第一和第二凹陷区域中执行选择性外延生长，以形成一个升高的外延层，其填充第一凹陷区域并延伸到半导体衬底的上表面之上的水平面并形成填充第二凹陷区域的凹陷外延层 凹陷区域。

公开(公告)号：US20060172501A1

公开(公告)日：2006-08-03

申请号：US11346107

申请日：2006-02-02

申请人： Tetsuji Ueno ,  Dong-suk Shin ,  Hwa-sung Rhee ,  Ho Lee ,  Seung-hwan Lee

发明人： Tetsuji Ueno ,  Dong-suk Shin ,  Hwa-sung Rhee ,  Ho Lee ,  Seung-hwan Lee

IPC分类号： H01L21/336

CPC分类号： H01L21/26506 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02658 ,  H01L21/02661

摘要： Provided is a method of manufacturing a high-quality silicon epitaxial growth. (SEG) layer on a highly doped silicon substrate. The method includes providing a semiconductor substrate including dopant areas with a predetermined concentration, implanting group IV ions into the substrate, cleaning the substrate using a chlorine-based gas, and forming a silicon epitaxial growth (SEG) layer on the substrate.

摘要翻译： 提供一种制造高质量硅外延生长的方法。 （SEG）层。 该方法包括提供包括具有预定浓度的掺杂剂区域的半导体衬底，将IV族离子注入到衬底中，使用氯基气体清洁衬底，以及在衬底上形成硅外延生长（SEG）层。

公开(公告)号：US07354835B2

公开(公告)日：2008-04-08

申请号：US11157521

申请日：2005-06-21

申请人： Dong-suk Shin ,  Hwa-sung Rhee ,  Ueno Tetsuji ,  Ho Lee ,  Seung-hwan Lee

发明人： Dong-suk Shin ,  Hwa-sung Rhee ,  Ueno Tetsuji ,  Ho Lee ,  Seung-hwan Lee

IPC分类号： H01L21/336

CPC分类号： H01L29/66636 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/165 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/7848

摘要： In a method of fabricating a CMOS transistor, and a CMOS transistor fabricated according to the method, the characteristics of first and second conductivity type MOS transistors are both simultaneously improved. At the same time, the fabrication process is simplified by reducing the number of masks required. The method includes amorphizing the active region of only the second conductivity type MOS transistor, and performing selective etching to form a first recessed region of a first depth in the active region of the first conductivity type MOS transistor and a second recessed region of a second depth that is greater than the first depth in the active region of the second conductivity type MOS transistor. Selective epitaxial growth is performed in the first and second recessed regions to form an elevated epitaxial layer that fills the first recessed region and extends to a level that is above the upper surface of the semiconductor substrate and to form a recessed epitaxial layer that fills the second recessed region.

摘要翻译： 在制造CMOS晶体管的方法和根据该方法制造的CMOS晶体管的情况下，第一和第二导电型MOS晶体管的特性都同时改善。 同时，通过减少所需掩模的数量来简化制造过程。 该方法包括仅使第二导电型MOS晶体管的有源区非晶化，并进行选择性蚀刻，以在第一导电类型MOS晶体管的有源区中形成第一深度的第一凹陷区域和第二深度的第二凹陷区域 大于第二导电类型MOS晶体管的有源区中的第一深度。 在第一和第二凹陷区域中执行选择性外延生长，以形成一个升高的外延层，其填充第一凹陷区域并延伸到半导体衬底的上表面之上的水平面并形成填充第二凹陷区域的凹陷外延层 凹陷区域。

公开(公告)号：US20050280098A1

公开(公告)日：2005-12-22

申请号：US11157521

申请日：2005-06-21

申请人： Dong-suk Shin ,  Hwa-sung Rhee ,  Ueno Tetsuji ,  Ho Lee ,  Seung-hwan Lee

发明人： Dong-suk Shin ,  Hwa-sung Rhee ,  Ueno Tetsuji ,  Ho Lee ,  Seung-hwan Lee

IPC分类号： H01L27/092 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/76

CPC分类号： H01L29/66636 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/165 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/7848

摘要： In a method of fabricating a CMOS transistor, and a CMOS transistor fabricated according to the method, the characteristics of first and second conductivity type MOS transistors are both simultaneously improved. At the same time, the fabrication process is simplified by reducing the number of masks required. The method includes amorphizing the active region of only the second conductivity type MOS transistor, and performing selective etching to form a first recessed region of a first depth in the active region of the first conductivity type MOS transistor and a second recessed region of a second depth that is greater than the first depth in the active region of the second conductivity type MOS transistor. Selective epitaxial growth is performed in the first and second recessed regions to form an elevated epitaxial layer that fills the first recessed region and extends to a level that is above the upper surface of the semiconductor substrate and to form a recessed epitaxial layer that fills the second recessed region.

摘要翻译： 在制造CMOS晶体管的方法和根据该方法制造的CMOS晶体管的情况下，第一和第二导电型MOS晶体管的特性都同时改善。 同时，通过减少所需掩模的数量来简化制造过程。 该方法包括仅使第二导电型MOS晶体管的有源区非晶化，并进行选择性蚀刻，以在第一导电类型MOS晶体管的有源区中形成第一深度的第一凹陷区域和第二深度的第二凹陷区域 大于第二导电类型MOS晶体管的有源区中的第一深度。 在第一和第二凹陷区域中执行选择性外延生长，以形成一个升高的外延层，其填充第一凹陷区域并延伸到半导体衬底的上表面之上的水平面并形成填充第二凹陷区域的凹陷外延层 凹陷区域。

公开(公告)号：US07619285B2

公开(公告)日：2009-11-17

申请号：US12029884

申请日：2008-02-12

申请人： Dong-suk Shin ,  Hwa-sung Rhee ,  Tetsuji Ueno ,  Ho Lee ,  Seung-hwan Lee

发明人： Dong-suk Shin ,  Hwa-sung Rhee ,  Tetsuji Ueno ,  Ho Lee ,  Seung-hwan Lee

IPC分类号： H01L29/772 ,  H01L21/8238

CPC分类号： H01L29/66636 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/165 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/7848

摘要： A CMOS transistor includes first and second conductivity type MOS transistors. The first conductivity type MOS transistor includes elevated source and drain regions which abut a channel region in a semiconductor substrate and which are formed by elevated epitaxial layers, each including a first epitaxial layer formed in a first recessed of the semiconductor substrate and a second epitaxial layer formed on the first epitaxial layer and extending to a level that is above an upper surface of the semiconductor substrate. The second conductivity type MOS transistor includes recessed source and drain regions which abut a channel region of the semiconductor substrate and which are formed by recessed epitaxial layers, each including a first epitaxial layer formed in a second recess of the semiconductor substrate and a second epitaxial layer formed in the second recess on the first epitaxial layer.

摘要翻译： CMOS晶体管包括第一和第二导电类型的MOS晶体管。 第一导电型MOS晶体管包括升高的源极和漏极区域，其邻接半导体衬底中的沟道区域并且由升高的外延层形成，每个包括形成在半导体衬底的第一凹部中的第一外延层和第二外延层 形成在所述第一外延层上并延伸到所述半导体衬底的上表面之上的水平。 第二导电型MOS晶体管包括凹陷的源极和漏极区域，其邻接半导体衬底的沟道区域并且由凹陷的外延层形成，每个包括形成在半导体衬底的第二凹槽中的第一外延层和第二外延层 形成在第一外延层上的第二凹槽中。