发明申请
- 专利标题: Delay locked loop circuit
- 专利标题(中): 延时锁定回路电路
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申请号: US11289753申请日: 2005-11-30
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公开(公告)号: US20060176091A1公开(公告)日: 2006-08-10
- 发明人: Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Toru Iwata , Takashi Hirata , Hideki Yoshii , Yasuyuki Doi , Makoto Hattori
- 申请人: Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Toru Iwata , Takashi Hirata , Hideki Yoshii , Yasuyuki Doi , Makoto Hattori
- 专利权人: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
- 当前专利权人: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
- 优先权: JP2005-033625 20050209; JP2005-264131 20050912
- 主分类号: H03L7/06
- IPC分类号: H03L7/06
摘要:
A delay element generates a delayed clock signal which transitions with a delay from a rising (or falling) of a reference clock signal by a delay amount determined based on an output of a loop filter. A signal generation circuit generates two signals which complementarily change according to rising and falling of the reference clock signal and a transition of the delayed clock signal. A charge pump circuit performs on the loop filter, according to these two signals, a push (or pull) operation during an interval extending from a rising (or falling) of the reference clock signal to the transition of the delayed clock signal and a pull (or push) operation during an interval extending from the transition of the delayed clock signal to a falling (or rising) of the reference clock signal.
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