公开(公告)号：US08847812B2

公开(公告)日：2014-09-30

申请号：US13589550

申请日：2012-08-20

Applicant: Shiro Dosho ,  Takuji Miki

Inventor： Shiro Dosho ,  Takuji Miki

IPC: H03M1/50 ,  G04F10/00 ,  H03K5/151

CPC classification number: G04F10/005 ,  H03K5/1515 ,  H03M1/50

Abstract: In a time-to-digital conversion stage, a time-to-digital conversion circuit outputs an n-bit digital signal, which represents an integer value ranging from −(2n-1−1) to +(2n-1−1), based on a phase difference between a first and a second signals input thereto; a time difference amplifier circuit amplifies the phase difference between the first and the second signals 2n-1 times, and outputs two signals having an amplified phase difference therebetween; a delay adjustment circuit adds a phase difference dependent on the digital signal to the two signals output from the time difference amplifier circuit, and outputs another two signals; an output detection circuit detects that the delay adjustment circuit has output the another two signals, and outputs a detection signal; and a storage circuit latches the digital signal in synchronism with the detection signal. Multi-stage coupling of the time-to-digital conversion stages forms a pipeline time-to-digital converter.

Abstract translation: 在时间数字转换阶段，时间数字转换电路输出表示从 - （2n-1-1）到+（2n-1-1）的整数值的n位数字信号， 基于输入到其的第一和第二信号之间的相位差; 时差放大器电路将第一和第二信号2n-1次之间的相位差放大倍数，并输出两个放大相位差的信号; 延迟调整电路将与数字信号相关的相位差与从时差放大器电路输出的两个信号相加，并输出另外两个信号; 输出检测电路检测出延迟调整电路输出了另外两个信号，并输出检测信号; 并且存储电路与检测信号同步地锁存数字信号。 时间 - 数字转换级的多级耦合形成流水线时间 - 数字转换器。

公开(公告)号：US08674864B2

公开(公告)日：2014-03-18

申请号：US13410964

申请日：2012-03-02

Applicant: Shiro Dosho

Inventor： Shiro Dosho

IPC: H03M3/00

CPC classification number: G06G7/186 ,  H03H11/12 ,  H03M3/39 ,  H03M3/454

Abstract: A high order integrator is configured using an operational amplifier, a first filter connected between an input terminal of the integrator and an inverted input terminal of the operational amplifier, and a second filter connected between the inverted input terminal and output terminal of the operational amplifier. The first filter includes n serially-connected first resistance elements, n−1 first capacitance elements each connected between each interconnecting node of the first resistance elements and the ground, and n−1 second resistance elements each connected between each interconnecting node of the first resistance elements and the ground. The second filter includes n serially-connected second capacitance elements, n−1 third resistance elements each connected between each interconnecting node of the second capacitance elements and the ground, and n−1 third capacitance elements each connected between each interconnecting node of the second capacitance elements and the ground.

Abstract translation: 高阶积分器使用运算放大器配置，第一滤波器连接在积分器的输入端和运算放大器的反相输入端之间，第二滤波器连接在运算放大器的反相输入端和输出端之间。 第一滤波器包括n个串联连接的第一电阻元件，每个连接在第一电阻元件的每个互连节点和地之间的n-1个第一电容元件，以及分别连接在第一电阻的每个互连节点之间的n-1个第二电阻元件 元素和地面。 第二滤波器包括n个串联连接的第二电容元件，n-1个第三电阻元件，每个连接在第二电容元件的每个互连节点和地之间; n-1个第三电容元件，每个连接在第二电容的每个互连节点之间 元素和地面。

公开(公告)号：US20120161999A1

公开(公告)日：2012-06-28

申请号：US13410991

申请日：2012-03-02

Applicant: Shiro DOSHO

Inventor： Shiro DOSHO

IPC: H03M1/12 ,  G06G7/18

CPC classification number: G06G7/186 ,  H03M3/40 ,  H03M3/454

Abstract: An oversampling A/D converter with a few operational amplifiers is configured using a complex second-order integrator including first and second second-order integrators and first and second coupling circuits configured to couple these integrators together. Each of the second-order integrators includes an operational amplifier, four resistance elements, and three capacitance elements. The first coupling circuit cross-couples one of two serially-connected capacitance elements inserted between the inverted input terminal and output terminal of the operational amplifier in the first second-order integrator to the counterpart in the second second-order integrator using two resistance elements. The second coupling circuit cross-couples the other capacitance element in the first second-order integrator to the counterpart in the second second-order integrator using two resistance elements.

Abstract translation: 具有几个运算放大器的过采样A / D转换器使用包括第一和第二二阶积分器的复合二阶积分器和被配置为将这些积分器耦合在一起的第一和第二耦合电路来配置。 每个二阶积分器包括运算放大器，四个电阻元件和三个电容元件。 第一耦合电路使用两个电阻元件将插入在第一二阶积分器中的运算放大器的反相输入端和输出端之间的两个串联连接的电容元件中的一个交叉到第二二阶积分器中的对应物。 第二耦合电路使用两个电阻元件将第一二阶积分器中的另一电容元件与第二二阶积分器中的对应物交叉。

公开(公告)号：US07920002B2

公开(公告)日：2011-04-05

申请号：US12133901

申请日：2008-06-05

Applicant: Shiro Sakiyama ,  Yusuke Tokunaga ,  Shiro Dosho ,  Akinori Matsumoto ,  Takashi Morie ,  Kazuaki Sogawa ,  Yukihiro Sasagawa ,  Masaya Sumita

Inventor： Shiro Sakiyama ,  Yusuke Tokunaga ,  Shiro Dosho ,  Akinori Matsumoto ,  Takashi Morie ,  Kazuaki Sogawa ,  Yukihiro Sasagawa ,  Masaya Sumita

IPC: H03K5/01

CPC classification number: H03K5/00006 ,  H03K5/13

Abstract: A high-level period of each of n first pulse signals partially or wholly overlaps a period during which all of n second pulse signals are at the low level. A high-level period of each of the n second pulse signals partially or wholly overlaps a period during which all of the n first pulse signals are at the low level. Each of n first drive transistors includes a source connected to a ground node, a drain connected to a first node, and a gate receiving a corresponding one of the first pulse signals. Each of n second drive transistors includes a source connected to the ground node, a drain connected to a second node, and a gate receiving a corresponding one of the second pulse signals. A current mirror circuit allows a current corresponding to a current flowing through the second node to flow through the first node.

Abstract translation: n个第一脉冲信号中的每一个的高电平周期部分或全部与在所有n个第二脉冲信号都处于低电平的期间重叠。 n个第二脉冲信号中的每一个的高电平周期部分地或完全地重叠在所有n个第一脉冲信号处于低电平的时段。 n个第一驱动晶体管中的每一个包括连接到接地节点的源极，连接到第一节点的漏极以及接收相应的一个第一脉冲信号的栅极。 n个第二驱动晶体管中的每一个包括连接到接地节点的源极，连接到第二节点的漏极和接收相应的一个第二脉冲信号的栅极。 电流镜电路允许对应于流过第二节点的电流的电流流过第一节点。

公开(公告)号：US20110018752A1

公开(公告)日：2011-01-27

申请号：US12899154

申请日：2010-10-06

Applicant: Masao TAKAYAMA ,  Kazuo Matsukawa ,  Yosuke Mitani ,  Shiro Dosho

Inventor： Masao TAKAYAMA ,  Kazuo Matsukawa ,  Yosuke Mitani ,  Shiro Dosho

IPC: H03M3/00 ,  H03M1/36

CPC classification number: H03M1/002 ,  H03M1/208 ,  H03M1/361

Abstract: In a flash A/D converter, a predictor predicts next analog input data based on a digital output signal from an A/D converter, and outputs prediction data. Based on the prediction data from the predictor, a controller turns on comparators having reference voltages near the prediction data, and in order to ensure a certain degree of A/D conversion accuracy even when the prediction fails, also turns on even-numbered comparators 103.2a (where a is 0 to 7), for example. In this manner, even when prediction of next analog input data fails, a 4-bit A/D converter can perform A/D conversion with 3-bit accuracy, while saving power consumption by reducing the number of comparators to be turned on.

Abstract translation: 在闪存A / D转换器中，预测器基于来自A / D转换器的数字输出信号预测下一个模拟输入数据，并输出预测数据。 基于来自预测器的预测数据，控制器打开具有靠近预测数据的参考电压的比较器，并且即使在预测失败时也确保一定程度的A / D转换精度，也打开偶数比较器103.2 a（其中a为0至7）。 以这种方式，即使当下一个模拟输入数据的预测失败时，四位A / D转换器也可以以3位精度执行A / D转换，同时通过减少比较器的数量来导通，从而节省功耗。

公开(公告)号：US07876166B2

公开(公告)日：2011-01-25

申请号：US12831715

申请日：2010-07-07

Applicant: Shiro Dosho ,  Shiro Sakiyama ,  Noriaki Takeda

Inventor： Shiro Dosho ,  Shiro Sakiyama ,  Noriaki Takeda

IPC: H03K3/03

CPC classification number: H03K3/0315

Abstract: A coupled ring oscillator includes n ring oscillators (20) each including m inverter circuits (10), and a phase-coupling loop (40) in which m×n phase-coupling circuits (30), each of which couples signal phases at two points in a certain phase mode, are connected with each other to form a loop. Connection points at which the inverter circuits (10) are connected with each other and the connection points at which the phase-coupling circuits (30) are connected with each other are connected bijectively; and each of the inverter circuits (10) is connected between two points that divide the phase-coupling circuits (30) into two parts at a certain ratio.

Abstract translation: 耦合环形振荡器包括n个环形振荡器（20），每个环形振荡器（20）包括m个逆变器电路（10）和相位耦合回路（40），其中m×n个相位耦合电路（30） 点在某一相位模式下，相互连接形成一个回路。 逆变器电路（10）彼此连接的连接点和相位耦合电路（30）彼此连接的连接点彼此连接; 并且每个逆变器电路（10）连接在将相耦合电路（30）以一定比例分成两部分的两个点之间。

公开(公告)号：US07633421B2

公开(公告)日：2009-12-15

申请号：US12093252

申请日：2007-07-30

Applicant: Shiro Dosho ,  Takashi Morie ,  Yusuke Tokunaga ,  Shiro Sakiyama

Inventor： Shiro Dosho ,  Takashi Morie ,  Yusuke Tokunaga ,  Shiro Sakiyama

IPC: H03M1/12

CPC classification number: H03M1/123 ,  H03M1/1215 ,  H03M1/56

Abstract: An A/D converter includes: a plurality of A/D conversion circuits (10 a, 10b); an input selection section (20) for selecting the A/D conversion circuit that is not executing A/D conversion to supply analog amounts obtained by sample-holding an input signal; and an output selection section (30) for selecting the A/D conversion circuit that is not executing A/D conversion to output digital amounts obtained from the selected one. Each A/D conversion circuit includes: an input memory portion (11) for sequentially storing the supplied analog amounts in a plurality of analog memory elements (111); an A/D conversion portion (12) having a plurality of A/D conversion elements (121) for converting the analog amounts stored in the analog memory elements to digital amounts; and a shift output portion (13), having a plurality of registers (131) receiving the digital amounts from the A/D conversion elements to hold the digital amounts, for shifting and outputting the digital amounts held in the registers.

Abstract translation: A / D转换器包括：多个A / D转换电路（10a，10b）; 输入选择部分（20），用于选择不执行A / D转换的A / D转换电路以提供通过采样保持输入信号获得的模拟量; 以及用于选择不执行A / D转换的A / D转换电路以输出从所选择的数字量获得的数字量的输出选择部分（30）。 每个A / D转换电路包括：用于在多个模拟存储器元件（111）中顺序地存储所提供的模拟量的输入存储器部分（11）。 具有用于将存储在模拟存储器元件中的模拟量转换为数字量的多个A / D转换元件的A / D转换部分（12） 以及移位输出部分（13），具有从A / D转换元件接收数字量以保持数字量的多个寄存器（131），用于移位和输出保存在寄存器中的数字量。

公开(公告)号：US07453313B2

公开(公告)日：2008-11-18

申请号：US11637687

申请日：2006-12-13

Applicant: Shiro Sakiyama ,  Yusuke Tokunaga ,  Shiro Dosho ,  Toru Iwata ,  Takashi Hirata

Inventor： Shiro Sakiyama ,  Yusuke Tokunaga ,  Shiro Dosho ,  Toru Iwata ,  Takashi Hirata

IPC: G06F3/02

CPC classification number: H02M3/07 ,  H03L7/0895 ,  H03L7/0896

Abstract: A charge pumping circuit includes a first switch for controlling one of push and pull operations in accordance with a first control signal; a current mirror circuit constructed from transistors each having a different polarity from the first switch; a second switch for controlling current input to the current mirror circuit in accordance with a second control signal, the second switch being constructed from a transistor having the same characteristic as a transistor used for constructing the first switch; a first MOS capacitor one end of which is connected to an input side of the current mirror circuit; a second MOS capacitor receiving, at one end thereof, a current concerned with the push and pull operations; and a voltage buffer connected to the first and second MOS capacitors. The other of the push and pull operations is performed with an output current of the current mirror circuit.

Abstract translation: 电荷泵浦电路包括：第一开关，用于根据第一控制信号控制推挽操作中的一个; 由与所述第一开关具有不同极性的晶体管构成的电流镜电路; 第二开关，用于根据第二控制信号控制到电流镜电路的电流输入，第二开关由具有与用于构造第一开关的晶体管相同的特性的晶体管构成; 第一MOS电容器，其一端连接到电流镜电路的输入侧; 在其一端接收与推挽操作有关的电流的第二MOS电容器; 以及连接到第一和第二MOS电容器的电压缓冲器。 推挽操作中的另一个用电流镜电路的输出电流进行。

公开(公告)号：US20080169948A1

公开(公告)日：2008-07-17

申请号：US11792081

申请日：2005-09-02

Applicant: Kouji Okamoto ,  Takashi Morie ,  Shiro Dosho ,  Hirokuni Fujiyama

Inventor： Kouji Okamoto ,  Takashi Morie ,  Shiro Dosho ,  Hirokuni Fujiyama

IPC: H03M1/06 ,  H03H11/04 ,  H03H11/20 ,  H03M1/10 ,  H03H11/12

CPC classification number: H03G5/16 ,  H03H11/1291 ,  H03H11/20

Abstract: In a filter adjustment circuit for an analog filter circuit such as a Gm-C filter, an input signal IS from a reference signal generation circuit 1 is inputted to a Gm-C filter 2 to be filtered and then converted by a conversion circuit 3 to a digital signal. A reference signal RS from the reference signal generation circuit 1 is converted by a conversion circuit 4 to a digital signal. The two converted signals are held in time series in a holding circuit 5. A timing generation circuit 6 generates an update timing signal en based on a reference time-series signal ref from the holding circuit 5. A control signal generation circuit 7 generates a control signal CS based on the reference time-series signal ref and a filter output time-series signal tgt, each from the holding circuit 5. The control signal CS is inputted to the Gm-C filter 2 in response to the update timing signal en to adjust the gain of the Gm-C filter 2. As a result, variations in the response characteristics of the Gm-C filter 2 are adjusted with high accuracy with a simple circuit structure.

Abstract translation: 在用于诸如Gm-C滤波器的模拟滤波器电路的滤波器调节电路中，来自参考信号产生电路1的输入信号IS被输入到要过滤的Gm-C滤波器2，然后由转换电路3转换成 数字信号。 来自参考信号发生电路1的参考信号RS由转换电路4转换成数字信号。 两个转换信号在保持电路5中保持时间序列。定时产生电路6基于来自保持电路5的基准时间序列信号ref产生更新定时信号en。控制信号产生电路7产生控制 基于参考时间序列信号ref的信号CS和来自保持电路5的滤波器输出时间序列信号tgt。控制信号CS响应于更新定时信号en至...而被输入到Gm-C滤波器2 调整Gm-C滤波器2的增益。结果，以简单的电路结构，高精度地调整Gm-C滤波器2的响应特性的变化。

公开(公告)号：US07388405B2

公开(公告)日：2008-06-17

申请号：US11513239

申请日：2006-08-31

Applicant: Yusuke Tokunaga ,  Shiro Sakiyama ,  Shiro Dosho ,  Yasuyuki Doi ,  Makoto Hattori

Inventor： Yusuke Tokunaga ,  Shiro Sakiyama ,  Shiro Dosho ,  Yasuyuki Doi ,  Makoto Hattori

IPC: H03K19/094 ,  H03K19/0175 ,  H03B1/00

CPC classification number: H03K19/018571 ,  H03F1/0261 ,  H03F3/505 ,  H03F2200/18 ,  H04L25/028

Abstract: A time required for an output voltage of a source follower to rise from Low to a predetermined voltage depends on a bias voltage. Therefore, by setting a converged voltage of an output voltage to be high by increasing the bias voltage, the time required to rise up to the predetermined voltage can be reduced. Therefore, a first source follower which is biased so that the converged value of the output voltage becomes a predetermined Hi voltage when an input data signal goes from Low to Hi, and a second source follower which is biased so as to become the Hi voltage after a period of one clock when an input data signal goes from Low to Hi, are used. The two source followers are operated with appropriate timing.

Abstract translation: 源极跟随器的输出电压从低电平上升到预定电压所需的时间取决于偏置电压。 因此，通过增加偏置电压来设定输出电压的收敛电压为高，可以降低上升到预定电压所需的时间。 因此，当输入数据信号从低电平变为高电平时，被偏压使得输出电压的会聚值变为预定的Hi电压的第一源极跟随器，以及被偏置以便成为Hi电压之后的第二源极跟随器 使用输入数据信号从低电平变为高电平时的一个时钟周期。 两个来源追随者在适当的时机运行。