- 专利标题: Inverting data on result bus to prepare for instruction in the next cycle for high frequency execution units
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申请号: US11056894申请日: 2005-02-11
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公开(公告)号: US20060184773A1公开(公告)日: 2006-08-17
- 发明人: Brian Curran , Ashutosh Goyal , Michael Vaden , David Webber
- 申请人: Brian Curran , Ashutosh Goyal , Michael Vaden , David Webber
- 主分类号: G06F9/44
- IPC分类号: G06F9/44
摘要:
A method of operating an arithmetic logic unit (ALU) by inverting a result of an operation to be executed during a current cycle in response to control signals from instruction decode logic which indicate that a later operation will require a complement of the result, wherein the result is inverted during the current cycle. The later operation may be a subtraction operation that immediately follows the first operation. The later instruction is decoded prior to the current cycle to control the inversion in the ALU. The ALU includes an adder, a rotator, and a data manipulation unit which invert the result during the current cycle in response to an invert control signal. The second operation subtracts the result during a subsequent cycle in which a carry control signal to the adder is enabled, and the rotator and the data manipulation unit are disabled. The ALU may be used in an execution unit of a microprocessor, such as a fixed-point unit.