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    Inverting data on result bus to prepare for instruction in the next cycle for high frequency execution units
    1.
    发明申请
    Inverting data on result bus to prepare for instruction in the next cycle for high frequency execution units 失效

    公开(公告)号：US20060184773A1

    公开(公告)日：2006-08-17

    申请号：US11056894

    申请日：2005-02-11

    申请人： Brian Curran ,  Ashutosh Goyal ,  Michael Vaden ,  David Webber

    发明人： Brian Curran ,  Ashutosh Goyal ,  Michael Vaden ,  David Webber

    IPC分类号： G06F9/44

    CPC分类号： G06F9/3001 ,  G06F9/3867

    摘要： A method of operating an arithmetic logic unit (ALU) by inverting a result of an operation to be executed during a current cycle in response to control signals from instruction decode logic which indicate that a later operation will require a complement of the result, wherein the result is inverted during the current cycle. The later operation may be a subtraction operation that immediately follows the first operation. The later instruction is decoded prior to the current cycle to control the inversion in the ALU. The ALU includes an adder, a rotator, and a data manipulation unit which invert the result during the current cycle in response to an invert control signal. The second operation subtracts the result during a subsequent cycle in which a carry control signal to the adder is enabled, and the rotator and the data manipulation unit are disabled. The ALU may be used in an execution unit of a microprocessor, such as a fixed-point unit.

    Instruction cracking and issue shortening based on instruction base fields, index fields, operand fields, and various other instruction text bits
    2.
    发明授权
    Instruction cracking and issue shortening based on instruction base fields, index fields, operand fields, and various other instruction text bits 有权
    基于指令字段，索引字段，操作数字段和各种其他指令文本位的指令破解和问题缩短

    公开(公告)号：US08464030B2

    公开(公告)日：2013-06-11

    申请号：US12757330

    申请日：2010-04-09

    申请人： Fadi Busaba ,  Brian Curran ,  Lee Eisen ,  Bruce Giamei ,  David Hutton

    发明人： Fadi Busaba ,  Brian Curran ,  Lee Eisen ,  Bruce Giamei ,  David Hutton

    IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/00

    CPC分类号： G06F9/3017 ,  G06F9/30032 ,  G06F9/30054 ,  G06F9/30058

    摘要： A method, information processing system, and computer program product crack and/or shorten computer executable instructions. At least one instruction is received. The at least on instruction is analyzed. An instruction type associated with the at least one instruction is identified. At least one of a base field, an index field, one or more operands, and a mask field of the instruction are analyzed. At least one of the following is then performed: the at least one instruction is organized into a set of unit of operation; and the at least one instruction is shortened. The set of unit of operations is then executed.

    摘要翻译： 一种方法，信息处理系统和计算机程序产品破解和/或缩短计算机可执行指令。 至少接收一条指令。 至少对指令进行分析。 识别与该至少一条指令相关联的指令类型。 分析指令的基本字段，索引字段，一个或多个操作数和掩码字段中的至少一个。 然后执行以下中的至少一个：将至少一个指令组织成一组操作单元; 并且至少一个指令被缩短。 然后执行一组操作单元。

    Instruction group formation and mechanism for SMT dispatch
    3.
    发明申请
    Instruction group formation and mechanism for SMT dispatch 失效
    SMT派遣指导小组组织和机制

    公开(公告)号：US20060101241A1

    公开(公告)日：2006-05-11

    申请号：US10965143

    申请日：2004-10-14

    申请人： Brian Curran ,  Brian Konigsburg ,  Hung Le ,  David Luick ,  Dung Nguyen

    发明人： Brian Curran ,  Brian Konigsburg ,  Hung Le ,  David Luick ,  Dung Nguyen

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3853 ,  G06F9/30145 ,  G06F9/382 ,  G06F9/3851 ,  G06F9/3885

    摘要： A more efficient method of handling instructions in a computer processor, by associating resource fields with respective program instructions wherein the resource fields indicate which of the processor hardware resources are required to carry out the program instructions, calculating resource requirements for merging two or more program instructions based on their resource fields, and determining resource availability for simultaneously executing the merged program instructions based on the calculated resource requirements. Resource vectors indicative of the required resource may be encoded into the resource fields, and the resource fields decoded at a later stage to derive the resource vectors. The resource fields can be stored in the instruction cache associated with the respective program instructions. The processor may operate in a simultaneous multithreading mode with different program instructions being part of different hardware threads. When the resource availability equals or exceeds the resource requirements for a group of instructions, those instructions can be dispatched simultaneously to the hardware resources. A start bit may be inserted in one of the program instructions to define the instruction group. The hardware resources may in particular be execution units such as a fixed-point unit, a load/store unit, a floating-point unit, or a branch processing unit.

    摘要翻译： 通过将资源字段与相应的程序指令相关联来处理计算机处理器中的指令的更有效的方法，其中资源字段指示需要哪个处理器硬件资源来执行程序指令，计算用于合并两个或多个程序指令的资源需求 并且基于所计算的资源需求来确定用于同时执行所合并的程序指令的资源可用性。 指示所需资源的资源矢量可以被编码到资源字段中，并且在稍后阶段解码资源字段以导出资源向量。 资源字段可以存储在与相应的程序指令相关联的指令高速缓存中。 处理器可以以同时多线程模式操作，其中不同的程序指令是不同硬件线程的一部分。 当资源可用性等于或超过一组指令的资源需求时，可以将这些指令同时发送到硬件资源。 可以在程序指令之一中插入起始位以定义指令组。 硬件资源可以特别地是诸如定点单元，加载/存储单元，浮点单元或分支处理单元之类的执行单元。

    Dual issuing of complex instruction set instructions
    5.
    发明授权
    Dual issuing of complex instruction set instructions 有权
    双重发出复杂的指令集指令

    公开(公告)号：US09104399B2

    公开(公告)日：2015-08-11

    申请号：US12645716

    申请日：2009-12-23

    申请人： Fadi Busaba ,  Brian Curran ,  Lee Eisen ,  Christian Jacobi ,  David A. Schroter ,  Eric Schwarz

    发明人： Fadi Busaba ,  Brian Curran ,  Lee Eisen ,  Christian Jacobi ,  David A. Schroter ,  Eric Schwarz

    IPC分类号： G06F15/00 ,  G06F9/30 ,  G06F9/40 ,  G06F9/38

    CPC分类号： G06F9/3001 ,  G06F9/30043 ,  G06F9/3017 ,  G06F9/3836 ,  G06F9/3867

    摘要： A system and method for issuing a processor instruction to multiple processing sections arranged in an out-of-order processing pipeline architecture. The multiple processing sections include a first execution unit with a pipeline length and a second execution unit operating upon data produced by the first execution unit. An instruction issue unit accepts a complex instruction that is cracked into respective micro-ops for the first execution unit and the second execution unit. The instruction issue unit issues the first micro-op to the first execution unit to produce intermediate data. The instruction issue unit then delays for a time period corresponding to the processing pipeline length of the first execution unit. After the delay, a second micro-op is issued to the second execution unit.

    摘要翻译： 一种用于向处理流水线结构排列的多个处理部分发出处理器指令的系统和方法。 多个处理部分包括具有流水线长度的第一执行单元和对由第一执行单元产生的数据进行操作的第二执行单元。 指令发布单元接受对于第一执行单元和第二执行单元破解为相应微操作的复杂指令。 指令发布单元向第一执行单元发出第一微操作以产生中间数据。 然后，指令发布单元延迟与第一执行单元的处理流水线长度对应的时间段。 在延迟之后，向第二执行单元发出第二个微操作。

    Instruction length based cracking for instruction of variable length storage operands
    8.
    发明授权
    Instruction length based cracking for instruction of variable length storage operands 有权
    指令长度为可变长度存储操作数指令的破解

    公开(公告)号：US08495341B2

    公开(公告)日：2013-07-23

    申请号：US12707163

    申请日：2010-02-17

    申请人： Fadi Busaba ,  Brian Curran ,  Bruce Giamei ,  Christian Jacobi ,  Wen Li

    发明人： Fadi Busaba ,  Brian Curran ,  Bruce Giamei ,  Christian Jacobi ,  Wen Li

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30032 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/3017

    摘要： A method, information processing system, and computer program product manage variable operand length instructions. At least one variable operand length instruction is received. The at least one variable operand length instruction is analyzed. A length of at least one operand in the variable operand length instruction is identified based on the analyzing. The at least one variable operand length instruction is organized into a set of unit of operations. The set of unit of operations are executed. The executing increases one or more performance metrics of the at least one variable operand length instruction.

    摘要翻译： 一种方法，信息处理系统和计算机程序产品管理可变操作数长度指令。 接收至少一个可变操作数长度指令。 分析至少一个可变操作数长度指令。 基于分析来识别可变操作数长度指令中的至少一个操作数的长度。 所述至少一个可变操作数长度指令被组织成一组操作单元。 执行操作单元的集合。 所述执行增加所述至少一个可变操作数长度指令的一个或多个性能度量。