公开(公告)号：US20060184773A1

公开(公告)日：2006-08-17

申请号：US11056894

申请日：2005-02-11

申请人： Brian Curran ,  Ashutosh Goyal ,  Michael Vaden ,  David Webber

发明人： Brian Curran ,  Ashutosh Goyal ,  Michael Vaden ,  David Webber

IPC分类号： G06F9/44

CPC分类号： G06F9/3001 ,  G06F9/3867

摘要： A method of operating an arithmetic logic unit (ALU) by inverting a result of an operation to be executed during a current cycle in response to control signals from instruction decode logic which indicate that a later operation will require a complement of the result, wherein the result is inverted during the current cycle. The later operation may be a subtraction operation that immediately follows the first operation. The later instruction is decoded prior to the current cycle to control the inversion in the ALU. The ALU includes an adder, a rotator, and a data manipulation unit which invert the result during the current cycle in response to an invert control signal. The second operation subtracts the result during a subsequent cycle in which a carry control signal to the adder is enabled, and the rotator and the data manipulation unit are disabled. The ALU may be used in an execution unit of a microprocessor, such as a fixed-point unit.

公开(公告)号：US20080301411A1

公开(公告)日：2008-12-04

申请号：US12189797

申请日：2008-08-12

申请人： Brian William Curran ,  Ashutosh Goyal ,  Michael Thomas Vaden ,  David Allan Webber

发明人： Brian William Curran ,  Ashutosh Goyal ,  Michael Thomas Vaden ,  David Allan Webber

IPC分类号： G06F9/302 ,  G06F9/312

CPC分类号： G06F9/3001 ,  G06F9/3867

摘要： A method of operating an arithmetic logic unit (ALU) by inverting a result of an operation to be executed during a current cycle in response to control signals from instruction decode logic which indicate that a later operation will require a complement of the result, wherein the result is inverted during the current cycle. The later operation may be a subtraction operation that immediately follows the first operation. The later instruction is decoded prior to the current cycle to control the inversion in the ALU. The ALU includes an adder, a rotator, and a data manipulation unit which invert the result during the current cycle in response to an invert control signal. The second operation subtracts the result during a subsequent cycle in which a carry control signal to the adder is enabled, and the rotator and the data manipulation unit are disabled. The ALU may be used in an execution unit of a microprocessor, such as a fixed-point unit.

摘要翻译： 一种通过使来自指令解码逻辑的控制信号反应在当前周期期间执行的操作的结果来操作算术逻辑单元（ALU）的方法，其指示稍后的操作将需要结果的补码，其中， 结果在当前周期内反转。 稍后的操作可以是紧跟在第一操作之后的减法操作。 后续指令在当前周期之前进行解码，以控制ALU中的反转。 ALU包括加法器，旋转器和数据操作单元，其响应于反转控制信号在当前周期内反转结果。 第二操作在随后的周期中减去结果，其中使能到加法器的进位控制信号，并且旋转器和数据操作单元被禁用。 ALU可以用在诸如定点单元的微处理器的执行单元中。

公开(公告)号：US07991816B2

公开(公告)日：2011-08-02

申请号：US12189797

申请日：2008-08-12

申请人： Brian William Curran ,  Ashutosh Goyal ,  Michael Thomas Vaden ,  David Allan Webber

发明人： Brian William Curran ,  Ashutosh Goyal ,  Michael Thomas Vaden ,  David Allan Webber

IPC分类号： G06F7/38

CPC分类号： G06F9/3001 ,  G06F9/3867

摘要： A method of operating an arithmetic logic unit (ALU) by inverting a result of an operation to be executed during a current cycle in response to control signals from instruction decode logic which indicate that a later operation will require a complement of the result, wherein the result is inverted during the current cycle. The later operation may be a subtraction operation that immediately follows the first operation. The later instruction is decoded prior to the current cycle to control the inversion in the ALU. The ALU includes an adder, a rotator, and a data manipulation unit which invert the result during the current cycle in response to an invert control signal. The second operation subtracts the result during a subsequent cycle in which a carry control signal to the adder is enabled, and the rotator and the data manipulation unit are disabled. The ALU may be used in an execution unit of a microprocessor, such as a fixed-point unit.

摘要翻译： 一种通过将当前周期内要执行的操作的结果与来自指令解码逻辑的控制信号相反的操作算术逻辑单元（ALU）的方法，该指令解码逻辑指示稍后的操作将需要结果的补码，其中， 结果在当前周期内反转。 稍后的操作可以是紧跟在第一操作之后的减法操作。 后续指令在当前周期之前进行解码，以控制ALU中的反转。 ALU包括加法器，旋转器和数据操作单元，其响应于反转控制信号在当前周期内反转结果。 第二操作在随后的周期中减去结果，其中使能到加法器的进位控制信号，并且旋转器和数据操作单元被禁用。 ALU可以用在诸如定点单元的微处理器的执行单元中。

公开(公告)号：US07523153B2

公开(公告)日：2009-04-21

申请号：US11057330

申请日：2005-02-11

申请人： Ashutosh Goyal

发明人： Ashutosh Goyal

IPC分类号： G06F7/507

CPC分类号： G06F7/508

摘要： A summing circuit for an adder decodes control signals to determine that the result should be manipulated, and generates a half-sum output which is used to produce a manipulated result based on the control signals. The half-sum output is combined with a previous carry bit to complete the sum operation. The control signals can invert the adder result, or force the result to be all 1's. These functions can be effectuated in a 3-way multiplexer that combines the operand inputs and control signals. For inversion, two separate logic circuits produce true and complement half-sums in parallel, and the appropriate half-sum is selected for the half-sum output. For a result of all 1's, a force—1 control signal pulls the half-sum output node to electrical ground and the final output is manipulated by gating the carry signals with the force—1 signal. The two functions are implemented without introducing additional delay.

摘要翻译： 用于加法器的求和电路解码控制信号以确定应该对结果进行处理，并产生用于产生基于控制信号的操纵结果的半和输出。 半和输出与先前的进位位组合，以完成和操作。 控制信号可以反转加法器结果，或强制结果为1。 这些功能可以在组合操作数输入和控制信号的3路多路复用器中实现。 对于反转，两个单独的逻辑电路并联产生真和补数半和，并且为半和输出选择适当的半和。 对于所有1的结果，力-1控制信号将半和输出节点拉到电地，并且通过用力-1信号门控进位信号来操纵最终输出。 这两个功能在不引入额外延迟的情况下实现。

公开(公告)号：US08429213B2

公开(公告)日：2013-04-23

申请号：US12360106

申请日：2009-01-26

申请人： Ashutosh Goyal

发明人： Ashutosh Goyal

IPC分类号： G06F7/50

CPC分类号： G06F7/508

摘要： A summing circuit for an adder decodes control signals to determine that the result should be manipulated, and generates a half-sum output which is used to produce a manipulated result based on the control signals. The half-sum output is combined with a previous carry bit to complete the sum operation. The control signals can invert the adder result, or force the result to be all 1's. These functions can be effectuated in a 3-way multiplexer that combines the operand inputs and control signals. For inversion, two separate logic circuits produce true and complement half-sums in parallel, and the appropriate half-sum is selected for the half-sum output. For a result of all 1's, a force_1 control signal pulls the half-sum output node to electrical ground and the final output is manipulated by gating the carry signals with the force_1 signal. The two functions are implemented without introducing additional delay.

摘要翻译： 用于加法器的求和电路解码控制信号以确定应该对结果进行处理，并产生用于产生基于控制信号的操纵结果的半和输出。 半和输出与先前的进位位组合，以完成和操作。 控制信号可以反转加法器结果，或强制结果为1。 这些功能可以在组合操作数输入和控制信号的3路多路复用器中实现。 对于反转，两个单独的逻辑电路并联产生真和补数半和，并且为半和输出选择适当的半和。 对于所有1的结果，force_1控制信号将半和输出节点拉到电接地，并且通过用force_1信号门控进位信号来操纵最终输出。 这两个功能在不引入额外延迟的情况下实现。

公开(公告)号：US07974913B1

公开(公告)日：2011-07-05

申请号：US12182900

申请日：2008-07-30

申请人： Vladimir Morozov ,  Ashutosh Goyal ,  Gauravdeep S. Sagar ,  Amit Manwani ,  Sami Haj Slimane ,  Dragan Dacic

发明人： Vladimir Morozov ,  Ashutosh Goyal ,  Gauravdeep S. Sagar ,  Amit Manwani ,  Sami Haj Slimane ,  Dragan Dacic

IPC分类号： G06Q40/00

CPC分类号： G06Q40/04

摘要： The disclosed technology involves estimating daily trading volume for a securities market for a next day, estimating daily trading volume for a particular security for a next day, and estimating intraday trading volume for a particular security for a next time bin in the current day.

摘要翻译： 所披露的技术包括估计第二天的证券市场的日交易量，估计第二天特定证券的日交易量，以及估计当天下一个仓位的特定证券的日内交易量。

公开(公告)号：US20090132631A1

公开(公告)日：2009-05-21

申请号：US12360106

申请日：2009-01-26

申请人： Ashutosh Goyal

发明人： Ashutosh Goyal

IPC分类号： G06F7/50

CPC分类号： G06F7/508

摘要： A summing circuit for an adder decodes control signals to determine that the result should be manipulated, and generates a half-sum output which is used to produce a manipulated result based on the control signals. The half-sum output is combined with a previous carry bit to complete the sum operation. The control signals can invert the adder result, or force the result to be all 1's. These functions can be effectuated in a 3-way multiplexer that combines the operand inputs and control signals. For inversion, two separate logic circuits produce true and complement half-sums in parallel, and the appropriate half-sum is selected for the half-sum output. For a result of all 1's, a force_1 control signal pulls the half-sum output node to electrical ground and the final output is manipulated by gating the carry signals with the force_1 signal. The two functions are implemented without introducing additional delay.

摘要翻译： 用于加法器的求和电路解码控制信号以确定应该对结果进行处理，并产生用于产生基于控制信号的操纵结果的半和输出。 半和输出与先前的进位位组合，以完成和操作。 控制信号可以反转加法器结果，或强制结果为1。 这些功能可以在组合操作数输入和控制信号的3路多路复用器中实现。 对于反转，两个单独的逻辑电路并联产生真和补数半和，并且为半和输出选择适当的半和。 对于所有1的结果，force_1控制信号将半和输出节点拉到电接地，并且通过用force_1信号门控进位信号来操纵最终输出。 这两个功能在不引入额外延迟的情况下实现。

公开(公告)号：US07509365B2

公开(公告)日：2009-03-24

申请号：US11056894

申请日：2005-02-11

申请人： Brian William Curran ,  Ashutosh Goyal ,  Michael Thomas Vaden ,  David Allan Webber

发明人： Brian William Curran ,  Ashutosh Goyal ,  Michael Thomas Vaden ,  David Allan Webber

IPC分类号： G06F7/38

CPC分类号： G06F9/3001 ,  G06F9/3867

摘要： A method of operating an arithmetic logic unit (ALU) by inverting a result of an operation to be executed during a current cycle in response to control signals from instruction decode logic which indicate that a later operation will require a complement of the result, wherein the result is inverted during the current cycle. The later operation may be a subtraction operation that immediately follows the first operation. The later instruction is decoded prior to the current cycle to control the inversion in the ALU. The ALU includes an adder, a rotator, and a data manipulation unit which invert the result during the current cycle in response to an invert control signal. The second operation subtracts the result during a subsequent cycle in which a carry control signal to the adder is enabled, and the rotator and the data manipulation unit are disabled. The ALU may be used in an execution unit of a microprocessor, such as a fixed-point unit.

摘要翻译： 一种通过将当前周期内要执行的操作的结果与来自指令解码逻辑的控制信号相反的操作算术逻辑单元（ALU）的方法，该指令解码逻辑指示稍后的操作将需要结果的补码，其中， 结果在当前周期内反转。 稍后的操作可以是紧跟在第一操作之后的减法操作。 后续指令在当前周期之前进行解码，以控制ALU中的反转。 ALU包括加法器，旋转器和数据操作单元，其响应于反转控制信号在当前周期内反转结果。 第二操作在随后的周期中减去结果，其中使能到加法器的进位控制信号，并且旋转器和数据操作单元被禁用。 ALU可以用在诸如定点单元的微处理器的执行单元中。

公开(公告)号：US20060184605A1

公开(公告)日：2006-08-17

申请号：US11057330

申请日：2005-02-11

申请人： Ashutosh Goyal

发明人： Ashutosh Goyal

IPC分类号： G06F7/50

CPC分类号： G06F7/508

摘要： A summing circuit for an adder decodes control signals to determine that the result should be manipulated, and generates a half-sum output which is used to produce a manipulated result based on the control signals. The half-sum output is combined with a previous carry bit to complete the sum operation. The control signals can invert the adder result, or force the result to be all 1's. These functions can be effectuated in a 3-way multiplexer that combines the operand inputs and control signals. For inversion, two separate logic circuits produce true and complement half-sums in parallel, and the appropriate half-sum is selected for the half-sum output. For a result of all 1's, a force—1 control signal pulls the half-sum output node to electrical ground and the final output is manipulated by gating the carry signals with the force—1 signal. The two functions are implemented without introducing additional delay.

摘要翻译： 用于加法器的求和电路解码控制信号以确定应该对结果进行处理，并产生用于产生基于控制信号的操纵结果的半和输出。 半和输出与先前的进位位组合，以完成和操作。 控制信号可以反转加法器结果，或强制结果为1。 这些功能可以在组合操作数输入和控制信号的3路多路复用器中实现。 对于反转，两个单独的逻辑电路并联产生真和补数半和，并且为半和输出选择适当的半和。 对于所有1的结果，力控制信号将半和输出节点拉到电接地，并且通过用力 - 1信号。 这两个功能在不引入额外延迟的情况下实现。