A control apparatus has a memory, a processor, an input/output controller, and an interrupt controller. The processor is accessible to the memory. The input/output controller starts to transfer data from an input/output device to write the data to a given area in the memory not through the processor, reads data out of the given area in the memory after last data is transferred, and issues an interrupt indicative of completion of data transfer after confirming that all of the transferred data has been written to the memory by confirming a response. The interrupt controller receives the interrupt from the input/output controller and transmits the interrupt to the processor.