- 专利标题: Low temperature load and bake
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申请号: US11433535申请日: 2006-05-12
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公开(公告)号: US20060201414A1公开(公告)日: 2006-09-14
- 发明人: Paul Brabant , Joe Italiano , Jianqing Wen
- 申请人: Paul Brabant , Joe Italiano , Jianqing Wen
- 主分类号: C30B23/00
- IPC分类号: C30B23/00 ; C30B25/00 ; C30B28/12 ; C30B28/14
摘要:
Methods are provided for low temperature, rapid baking to remove impurities from a semiconductor surface prior to in-situ deposition. Advantageously, a short, low temperature process consumes very little of the thermal budget, such that the process is suitable for advanced, high density circuits with shallow junctions. Furthermore, throughput is greatly improved by the low temperature bake, particularly in combination with low temperature plasma cleaning and low temperature wafer loading prior to the bake, and deposition after the bake at temperatures lower than conventional epitaxial deposition. The process enables epitaxial deposition of silicon-containing layers over semiconductor surfaces, particularly enabling epitaxial deposition over a silicon germanium base layer. By use of a low-temperature bake, the silicon germanium base layer can be cleaned to facilitate further epitaxial deposition without relaxing the strained crystal structure of the silicon germanium.
公开/授权文献
- US07462239B2 Low temperature load and bake 公开/授权日:2008-12-09
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