公开(公告)号：US20060201414A1

公开(公告)日：2006-09-14

申请号：US11433535

申请日：2006-05-12

申请人： Paul Brabant ,  Joe Italiano ,  Jianqing Wen

发明人： Paul Brabant ,  Joe Italiano ,  Jianqing Wen

IPC分类号： C30B23/00 ,  C30B25/00 ,  C30B28/12 ,  C30B28/14

CPC分类号： C23C16/4408 ,  C23C16/0209 ,  C23C16/0227 ,  C23C16/4405 ,  C30B25/02 ,  C30B25/18 ,  C30B29/30 ,  C30B31/00 ,  H01L21/02046 ,  H01L21/02052 ,  Y10T117/10 ,  Y10T117/1004 ,  Y10T117/1008

摘要： Methods are provided for low temperature, rapid baking to remove impurities from a semiconductor surface prior to in-situ deposition. Advantageously, a short, low temperature process consumes very little of the thermal budget, such that the process is suitable for advanced, high density circuits with shallow junctions. Furthermore, throughput is greatly improved by the low temperature bake, particularly in combination with low temperature plasma cleaning and low temperature wafer loading prior to the bake, and deposition after the bake at temperatures lower than conventional epitaxial deposition. The process enables epitaxial deposition of silicon-containing layers over semiconductor surfaces, particularly enabling epitaxial deposition over a silicon germanium base layer. By use of a low-temperature bake, the silicon germanium base layer can be cleaned to facilitate further epitaxial deposition without relaxing the strained crystal structure of the silicon germanium.

公开(公告)号：US20060130743A1

公开(公告)日：2006-06-22

申请号：US11352738

申请日：2006-02-10

申请人： Paul Brabant ,  Joe Italiano ,  Jianqing Wen

发明人： Paul Brabant ,  Joe Italiano ,  Jianqing Wen

IPC分类号： C30B23/00 ,  C30B25/00 ,  C30B28/14 ,  C30B11/00 ,  C30B28/12

CPC分类号： C23C16/4408 ,  C23C16/0209 ,  C23C16/0227 ,  C23C16/4405 ,  C30B25/02 ,  C30B25/18 ,  C30B29/30 ,  C30B31/00 ,  H01L21/02046 ,  H01L21/02052 ,  Y10T117/10 ,  Y10T117/1004 ,  Y10T117/1008

摘要： Methods are provided for low temperature, rapid baking to remove impurities from a semiconductor surface prior to in-situ deposition. Advantageously, a short, low temperature process consumes very little of the thermal budget, such that the process is suitable for advanced, high density circuits with shallow junctions. Furthermore, throughput is greatly improved by the low temperature bake, particularly in combination with low temperature plasma cleaning and low temperature wafer loading prior to the bake, and deposition after the bake at temperatures lower than conventional epitaxial deposition. The process enables epitaxial deposition of silicon-containing layers over semiconductor surfaces, particularly enabling epitaxial deposition over a silicon germanium base layer. By use of a low-temperature bake, the silicon germanium base layer can be cleaned to facilitate further epitaxial deposition without relaxing the strained crystal structure of the silicon germanium.