The invention relates to an integrated circuit memory unit comprising: a memory cell, a switched bulk DC voltage source and a plurality of wordline-controlled transistors. Each of wordline-controlled transistors has a bulk connected to the switched bulk DC voltage source. When the data bit is read from the memory cell or the data bit is written into the memory cell, the bulks of the wordline-controlled transistors are switched to a first voltage level from the switched bulk DC voltage source so as to increase the drain current and obtain faster operation speed. When in an idle mode, the bulks of the wordline-controlled transistors are switched to a second voltage level from the switched bulk DC voltage source so as to obtain higher threshold voltage and decrease the leakage current.