发明申请
US20060267173A1 Integrated circuit package having stacked integrated circuits and method therefor 审中-公开
具有堆叠集成电路的集成电路封装及其方法

Integrated circuit package having stacked integrated circuits and method therefor
摘要:
Improved techniques for stacking integrated circuit dies within an integrated circuit package are disclosed. These improved techniques allow greater stacking density of integrated circuit dies within an integrated circuit package. Additionally, the improved stacking techniques permit conventional bonding techniques for electrical connection of the various integrated circuit dies to each other or to a substrate. These improved approaches are particularly useful for stacking same size (and often same function) integrated circuit dies within integrated circuit packages. One example of such an integrated circuit package is a non-volatile memory integrated circuit package that contains multiple, like-sized memory storage integrated circuit dies arranged in a stack.
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