公开(公告)号：US20060267173A1

公开(公告)日：2006-11-30

申请号：US11140608

申请日：2005-05-26

申请人： Hem Takiar ,  Shrikar Bhagath ,  Ken Ming Wang

发明人： Hem Takiar ,  Shrikar Bhagath ,  Ken Ming Wang

IPC分类号： H01L23/02

CPC分类号： H01L25/0657 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/01004 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： Improved techniques for stacking integrated circuit dies within an integrated circuit package are disclosed. These improved techniques allow greater stacking density of integrated circuit dies within an integrated circuit package. Additionally, the improved stacking techniques permit conventional bonding techniques for electrical connection of the various integrated circuit dies to each other or to a substrate. These improved approaches are particularly useful for stacking same size (and often same function) integrated circuit dies within integrated circuit packages. One example of such an integrated circuit package is a non-volatile memory integrated circuit package that contains multiple, like-sized memory storage integrated circuit dies arranged in a stack.

摘要翻译： 公开了用于在集成电路封装内堆叠集成电路管芯的改进的技术。 这些改进的技术允许集成电路封装内的集成电路管芯的堆叠密度更高。 此外，改进的堆叠技术允许用于将各种集成电路管芯彼此或与衬底电连接的常规焊接技术。 这些改进的方法对于在集成电路封装内堆叠相同尺寸（并且通常是相同功能的）集成电路管芯特别有用。 这种集成电路封装的一个例子是非易失性存储器集成电路封装，其包含堆叠地布置的多个相同大小的存储器集成电路管芯。

公开(公告)号：US20070004097A1

公开(公告)日：2007-01-04

申请号：US11171819

申请日：2005-06-30

申请人： Cheemen Yu ,  Ken Ming Wang ,  Chin-Tien Chiu ,  Chih-Chin Liao ,  Han-Shiao Chen

发明人： Cheemen Yu ,  Ken Ming Wang ,  Chin-Tien Chiu ,  Chih-Chin Liao ,  Han-Shiao Chen

IPC分类号： H01L21/82

CPC分类号： H05K1/0271 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/48 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3511 ,  H05K1/0224 ,  H05K1/0253 ,  H05K2201/09681 ,  H05K2201/0969 ,  H05K2201/09781 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A dummy circuit pattern is disclosed on a surface of a substrate for a semiconductor package. The dummy circuit pattern includes a plurality of straight line segments and a plurality of interrupt patterns to breakup one or more of the straight line segments. The interrupt patterns are provided so as to not electrically isolate areas of the dummy pattern, thus providing electrical continuity across the dummy circuit pattern.

摘要翻译： 在半导体封装用基板的表面上公开了虚设电路图案。 虚拟电路图案包括多条直线段和多条中断模式，以分解一条或多条直线段。 提供中断模式，以便不电隔离虚设图案的区域，从而在虚拟电路图案上提供电连续性。