Invention Application
US20060277398A1 Method and apparatus for instruction latency tolerant execution in an out-of-order pipeline
审中-公开
用于在无序流水线中执行指令等待时间的方法和装置
- Patent Title: Method and apparatus for instruction latency tolerant execution in an out-of-order pipeline
- Patent Title (中): 用于在无序流水线中执行指令等待时间的方法和装置
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Application No.: US11145409Application Date: 2005-06-03
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Publication No.: US20060277398A1Publication Date: 2006-12-07
- Inventor: Haitham Akkary , Ravi Rajwar , Srikanth Srinivasan , Christopher Wilkerson
- Applicant: Haitham Akkary , Ravi Rajwar , Srikanth Srinivasan , Christopher Wilkerson
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Main IPC: G06F9/44
- IPC: G06F9/44

Abstract:
A method and apparatus for setting aside a long-latency micro-operation from a reorder buffer is disclosed. In one embodiment, a long-latency micro-operation would conventionally stall a reorder buffer. Therefore a secondary buffer may be used to temporarily store that long-latency micro-operation, and other micro-operations depending from it, until that long-latency micro-operation is ready to execute. These micro-operations may then be reintroduced into the reorder buffer for execution. The use of poisoned bits may be used to ensure correct retirement of register values merged from both pre- and post-execution of the micro-operations which were set aside in the secondary buffer.
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