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    Method and apparatus for instruction latency tolerant execution in an out-of-order pipeline
    1.
    发明申请
    Method and apparatus for instruction latency tolerant execution in an out-of-order pipeline 审中-公开
    用于在无序流水线中执行指令等待时间的方法和装置

    公开(公告)号：US20060277398A1

    公开(公告)日：2006-12-07

    申请号：US11145409

    申请日：2005-06-03

    申请人： Haitham Akkary ,  Ravi Rajwar ,  Srikanth Srinivasan ,  Christopher Wilkerson

    发明人： Haitham Akkary ,  Ravi Rajwar ,  Srikanth Srinivasan ,  Christopher Wilkerson

    IPC分类号： G06F9/44

    CPC分类号： G06F9/3836 ,  G06F9/3814 ,  G06F9/383 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863

    摘要： A method and apparatus for setting aside a long-latency micro-operation from a reorder buffer is disclosed. In one embodiment, a long-latency micro-operation would conventionally stall a reorder buffer. Therefore a secondary buffer may be used to temporarily store that long-latency micro-operation, and other micro-operations depending from it, until that long-latency micro-operation is ready to execute. These micro-operations may then be reintroduced into the reorder buffer for execution. The use of poisoned bits may be used to ensure correct retirement of register values merged from both pre- and post-execution of the micro-operations which were set aside in the secondary buffer.

    摘要翻译： 公开了一种用于从重排序缓冲器中排除长延迟微操作的方法和装置。 在一个实施例中，长时间延迟微操作通常会阻止重新排序缓冲器。 因此，可以使用辅助缓冲器来临时存储长延迟微操作以及依赖于其的微操作，直到长时间延迟微操作准备好执行。 然后可以将这些微操作重新引入重排序缓冲器中以供执行。 可以使用中毒的位来确保正确地退出从辅助缓冲器中放置的微操作执行之前和之后合并的寄存器值。

    Critical section detection and prediction mechanism for hardware lock elision
    5.
    发明授权
    Critical section detection and prediction mechanism for hardware lock elision 有权
    硬件锁定检测的关键部分检测和预测机制

    公开(公告)号：US08190859B2

    公开(公告)日：2012-05-29

    申请号：US11599009

    申请日：2006-11-13

    申请人： Haitham Akkary ,  Ravi Rajwar ,  Srikanth T. Srinivasan

    发明人： Haitham Akkary ,  Ravi Rajwar ,  Srikanth T. Srinivasan

    IPC分类号： G06F12/00

    CPC分类号： G06F9/3865 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/528

    摘要： A method and apparatus for detecting lock instructions and lock release instruction, as well as predicting critical sections is herein described. A lock instruction is detected with detection logic, which potentially resides in decode logic. A lock instruction entry associated with the lock instruction is stored/created. Address locations and values to be written to those address location of subsequent potential lock release instruction are compared to the address loaded from by the lock instruction and the value load by the lock instruction. If the addresses and values match, it is determined that the lock release instruction matches the lock instruction. A prediction entry stores a reference to the lock instruction, such as a last instruction pointer (LIP), and an associated value to represent the lock instruction is to be elided upon subsequent detection, if it is determined that the lock release instruction matches the lock instruction.

    摘要翻译： 这里描述了用于检测锁定指令和锁定释放指令以及预测关键部分的方法和装置。 检测逻辑检测到锁定指令，这可能存在于解码逻辑中。 存储/创建与锁定指令相关联的锁定指令条目。 将要写入后续潜在锁定释放指令的地址位置的地址位置和值与通过锁定指令加载的地址和锁定指令的值负载进行比较。 如果地址和值匹配，则确定锁定释放指令与锁定指令匹配。 预测条目存储对诸如最后指令指针（LIP）的锁定指令的引用，并且如果确定锁定解除指令与锁定相匹配，则在后续检测时将要消除表示锁定指令的关联值 指令。

    Transactional memory virtualization
    7.
    发明申请
    Transactional memory virtualization 有权
    事务性内存虚拟化

    公开(公告)号：US20070239942A1

    公开(公告)日：2007-10-11

    申请号：US11394622

    申请日：2006-03-30

    申请人： Ravi Rajwar ,  Haitham Akkary ,  Konrad Lai

    发明人： Ravi Rajwar ,  Haitham Akkary ,  Konrad Lai

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0842 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3859 ,  G06F9/467

    摘要： Methods and apparatus to provide transactional memory execution in a virtualized mode are described. In one embodiment, data corresponding to a transactional memory access request may be stored in a portion of a memory after an operation corresponding to the transactional memory access request causes an overflow and a stored value may be updated for an occurrence of the overflow.

    摘要翻译： 描述了以虚拟化模式提供事务性存储器执行的方法和装置。 在一个实施例中，对应于事务存储器访问请求的数据可以在与事务存储器访问请求相对应的操作引起溢出并且可以针对溢出的发生更新存储的值之后存储在存储器的一部分中。

    LATE LOCK ACQUIRE MECHANISM FOR HARDWARE LOCK ELISION (HLE)
    10.
    发明申请
    LATE LOCK ACQUIRE MECHANISM FOR HARDWARE LOCK ELISION (HLE) 有权
    锁定锁定机构（HLE）

    公开(公告)号：US20090119459A1

    公开(公告)日：2009-05-07

    申请号：US11936249

    申请日：2007-11-07

    申请人： Haitham Akkary ,  Ravi Rajwar ,  Srikanth T. Srinivasan

    发明人： Haitham Akkary ,  Ravi Rajwar ,  Srikanth T. Srinivasan

    IPC分类号： G06F12/08 ,  G06F12/00

    CPC分类号： G06F9/526 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F12/0815

    摘要： A method and apparatus for a late lock acquire mechanism is herein described. In response to detecting a late-lock acquire event, such as expiration of a timer, a full cachet set, and an irrevocable event, a late-lock acquire may be initiated. Consecutive critical sections are stalled until a late-lock acquire is completed utilizing fields of access buffer entries associated with consecutive critical section operations.

    摘要翻译： 这里描述了一种用于后期锁定获取机制的方法和装置。 响应于检测到延迟获取事件，例如定时器的到期，完整的记录集和不可撤销的事件，可以启动延迟锁定获取。 连续的关键部分被停止，直到使用与连续关键部分操作相关联的访问缓冲器条目的字段来完成延迟锁定获取。