- 专利标题: Semiconductor memory
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申请号: US11513394申请日: 2006-08-31
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公开(公告)号: US20060291297A1公开(公告)日: 2006-12-28
- 发明人: Naoharu Shinozaki , Yasurou Matsuzaki
- 申请人: Naoharu Shinozaki , Yasurou Matsuzaki
- 专利权人: FUJITSU LIMITED
- 当前专利权人: FUJITSU LIMITED
- 优先权: JP2002-205313 20020715
- 主分类号: G11C7/10
- IPC分类号: G11C7/10
摘要:
A partial area for retaining data during low power consumption mode is composed of a single first memory cell out of a plurality of memory cells connected to a bit line. An operation control circuit operates any of the memory cells selected in accordance with an address signal during normal operation mode for performing a read operation and a write operation. The operation control circuit keeps latching data retained by the first memory cell in the partial area into a sense amplifier during the low power consumption mode. This eliminates the need for a refresh operation for retaining the data in the first memory cell during the low power consumption mode. Since the data can be retained without a refresh operation, it is possible to reduce the power consumption during the low power consumption mode.
公开/授权文献
- US07295483B2 Semiconductor memory 公开/授权日:2007-11-13
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