公开(公告)号：US06498524B1

公开(公告)日：2002-12-24

申请号：US09706731

申请日：2000-11-07

申请人： Kenichi Kawasaki ,  Yasuharu Sato ,  Terumasa Kitahara ,  Masao Nakano ,  Masao Taguchi ,  Yoshihiro Takemae ,  Yasurou Matsuzaki ,  Koichi Nishimura ,  Yoshinori Okajima ,  Naoharu Shinozaki ,  Hiroko Douchi

发明人： Kenichi Kawasaki ,  Yasuharu Sato ,  Terumasa Kitahara ,  Masao Nakano ,  Masao Taguchi ,  Yoshihiro Takemae ,  Yasurou Matsuzaki ,  Koichi Nishimura ,  Yoshinori Okajima ,  Naoharu Shinozaki ,  Hiroko Douchi

IPC分类号： H03L708

CPC分类号： G11C7/106 ,  G06F13/4243 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/002 ,  G11C2207/108 ,  H03K5/133 ,  H03K2005/00058 ,  H03L7/0805 ,  H03L7/0814

摘要： Disclosed is a semiconductor device for outputting an output signal with a given phase held relative to an external clock despite a difference in characteristic, a change in temperature, and a fluctuation in supply voltage. The semiconductor device comprises an input circuit for inputting the external clock and outputting a reference signal, an output circuit for receiving an output timing signal and outputting an output signal according to the timing of the output timing signal, and an output timing control circuit for controlling the output timing so that the output signal exhibits a given phase relative to the external clock. The output timing control circuit includes a delay circuit for delaying the reference signal by a specified magnitude and generating an output timing signal, a phase comparison circuit for comparing the phase of the output timing signal with the phase of the reference signal, and a delay control circuit for specifying the magnitude of a delay to be produced by the delay circuit according to the result of comparison performed by the phase comparison circuit.

摘要翻译： 公开了一种用于输出具有相对于外部时钟保持的给定相位的输出信号的半导体器件，尽管特性差，温度变化和电源电压波动。 该半导体器件包括用于输入外部时钟并输出参考信号的输入电路，用于接收输出定时信号并根据输出定时信号的定时输出输出信号的输出电路和用于控制的输出定时控制电路 输出定时，使得输出信号相对于外部时钟呈现给定的相位。 输出定时控制电路包括用于将参考信号延迟指定幅度并产生输出定时信号的延迟电路，用于将输出定时信号的相位与参考信号的相位进行比较的相位比较电路和延迟控制 电路，用于根据由相位比较电路执行的比较结果来指定由延迟电路产生的延迟的大小。

公开(公告)号：US06298004B1

公开(公告)日：2001-10-02

申请号：US08892790

申请日：1997-07-15

申请人： Kenichi Kawasaki ,  Yasuharu Sato ,  Terumasa Kitahara ,  Masao Nakano ,  Masao Taguchi ,  Yoshihiro Takemae ,  Yasurou Matsuzaki ,  Koichi Nishimura ,  Yoshinori Okajima ,  Naoharu Shinozaki ,  Hiroko Douchi

发明人： Kenichi Kawasaki ,  Yasuharu Sato ,  Terumasa Kitahara ,  Masao Nakano ,  Masao Taguchi ,  Yoshihiro Takemae ,  Yasurou Matsuzaki ,  Koichi Nishimura ,  Yoshinori Okajima ,  Naoharu Shinozaki ,  Hiroko Douchi

IPC分类号： G11C800

CPC分类号： G11C7/106 ,  G06F13/4243 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/002 ,  G11C2207/108 ,  H03K5/133 ,  H03K2005/00058 ,  H03L7/0805 ,  H03L7/0814

摘要： Disclosed is a semiconductor device for outputting an output signal with a given phase held relative to an external clock despite a difference in characteristic, a change in temperature, and a fluctuation in supply voltage. The semiconductor device comprises an input circuit for inputting the external clock and outputting a reference signal, an output circuit for receiving an output timing signal and outputting an output signal according to the timing of the output timing signal, and an output timing control circuit for controlling the output timing so that the output signal exhibits a given phase relative to the external clock. The output timing control circuit includes a delay circuit for delaying the reference signal by a specified magnitude and generating an output timing signal, a phase comparison circuit for comparing the phase of the output timing signal with the phase of the reference signal, and a delay control circuit for specifying the magnitude of a delay to be produced by the delay circuit according to the result of comparison performed by the phase comparison circuit.

摘要翻译： 公开了一种用于输出具有相对于外部时钟保持的给定相位的输出信号的半导体器件，尽管特性差，温度变化和电源电压波动。 该半导体器件包括用于输入外部时钟并输出参考信号的输入电路，用于接收输出定时信号并根据输出定时信号的定时输出输出信号的输出电路和用于控制的输出定时控制电路 输出定时，使得输出信号相对于外部时钟呈现给定的相位。 输出定时控制电路包括用于将参考信号延迟指定幅度并产生输出定时信号的延迟电路，用于将输出定时信号的相位与参考信号的相位进行比较的相位比较电路和延迟控制 电路，用于根据由相位比较电路执行的比较结果来指定由延迟电路产生的延迟的大小。

公开(公告)号：US20070153613A1

公开(公告)日：2007-07-05

申请号：US11715851

申请日：2007-03-09

申请人： Naoharu Shinozaki ,  Yasurou Matsuzaki

发明人： Naoharu Shinozaki ,  Yasurou Matsuzaki

IPC分类号： G11C5/14

CPC分类号： G11C11/40607 ,  G11C7/08 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40622 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4091 ,  G11C2207/2227 ,  G11C2211/4067 ,  G11C2211/4068

摘要： A partial area for retaining data during low power consumption mode is composed of a single first memory cell out of a plurality of memory cells connected to a bit line. An operation control circuit operates any of the memory cells selected in accordance with an address signal during normal operation mode for performing a read operation and a write operation. The operation control circuit keeps latching data retained by the first memory cell in the partial area into a sense amplifier during the low power consumption mode. This eliminates the need for a refresh operation for retaining the data in the first memory cell during the low power consumption mode. Since the data can be retained without a refresh operation, it is possible to reduce the power consumption during the low power consumption mode.

摘要翻译： 在低功耗模式期间用于保留数据的部分区域由连接到位线的多个存储单元中的单个第一存储单元组成。 操作控制电路在正常操作模式期间操作根据地址信号选择的任何存储单元，以执行读操作和写操作。 操作控制电路在低功耗模式期间将由部分区域中的第一存储单元保留的数据保持为读出放大器。 这消除了在低功耗模式期间需要用于将数据保持在第一存储单元中的刷新操作。 由于可以在不进行刷新操作的情况下保持数据，因此可以在低功耗模式下降低功耗。

公开(公告)号：US07317650B2

公开(公告)日：2008-01-08

申请号：US11715851

申请日：2007-03-09

申请人： Naoharu Shinozaki ,  Yasurou Matsuzaki

发明人： Naoharu Shinozaki ,  Yasurou Matsuzaki

IPC分类号： G11C7/00

CPC分类号： G11C11/40607 ,  G11C7/08 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40622 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4091 ,  G11C2207/2227 ,  G11C2211/4067 ,  G11C2211/4068

摘要： A partial area for retaining data during low power consumption mode is composed of a single first memory cell out of a plurality of memory cells connected to a bit line. An operation control circuit operates any of the memory cells selected in accordance with an address signal during normal operation mode for performing a read operation and a write operation. The operation control circuit keeps latching data retained by the first memory cell in the partial area into a sense amplifier during the low power consumption mode. This eliminates the need for a refresh operation for retaining the data in the first memory cell during the low power consumption mode. Since the data can be retained without a refresh operation, it is possible to reduce the power consumption during the low power consumption mode.

摘要翻译： 在低功耗模式期间用于保留数据的部分区域由连接到位线的多个存储单元中的单个第一存储单元组成。 操作控制电路在正常操作模式期间操作根据地址信号选择的任何存储单元，以执行读操作和写操作。 操作控制电路在低功耗模式期间将由部分区域中的第一存储单元保留的数据保持为读出放大器。 这消除了在低功耗模式期间需要用于将数据保持在第一存储单元中的刷新操作。 由于可以在不进行刷新操作的情况下保持数据，因此可以在低功耗模式下降低功耗。

公开(公告)号：US07209402B2

公开(公告)日：2007-04-24

申请号：US10968811

申请日：2004-10-20

申请人： Naoharu Shinozaki ,  Yasurou Matsuzaki

发明人： Naoharu Shinozaki ,  Yasurou Matsuzaki

IPC分类号： G11C7/00

CPC分类号： G11C11/40607 ,  G11C7/08 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40622 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4091 ,  G11C2207/2227 ,  G11C2211/4067 ,  G11C2211/4068

摘要： A partial area for retaining data during low power consumption mode is composed of a single first memory cell out of a plurality of memory cells connected to a bit line. An operation control circuit operates any of the memory cells selected in accordance with an address signal during normal operation mode for performing a read operation and a write operation. The operation control circuit keeps latching data retained by the first memory cell in the partial area into a sense amplifier during the low power consumption mode. This eliminates the need for a refresh operation for retaining the data in the first memory cell during the low power consumption mode. Since the data can be retained without a refresh operation, it is possible to reduce the power consumption during the low power consumption mode.

公开(公告)号：US20050242864A1

公开(公告)日：2005-11-03

申请号：US11055784

申请日：2005-02-11

申请人： Kenichi Kawasaki ,  Yasuharu Sato ,  Terumasa Kitahara ,  Masao Nakano ,  Masao Taguchi ,  Yoshihiro Takemae ,  Yasurou Matsuzaki ,  Koichi Nishimura ,  Yoshinori Okajima ,  Naoharu Shinozaki ,  Hiroko Douchi

发明人： Kenichi Kawasaki ,  Yasuharu Sato ,  Terumasa Kitahara ,  Masao Nakano ,  Masao Taguchi ,  Yoshihiro Takemae ,  Yasurou Matsuzaki ,  Koichi Nishimura ,  Yoshinori Okajima ,  Naoharu Shinozaki ,  Hiroko Douchi

IPC分类号： G06F13/42 ,  G11C7/10 ,  G11C7/22 ,  H03H11/26 ,  H03K5/00 ,  H03K5/13 ,  H03L7/081

CPC分类号： G11C7/106 ,  G06F13/4243 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/002 ,  G11C2207/108 ,  H03K5/133 ,  H03K2005/00058 ,  H03L7/0805 ,  H03L7/0814

摘要： Disclosed is a semiconductor device for outputting an output signal with a given phase held relative to an external clock despite a difference in characteristic, a change in temperature, and a fluctuation in supply voltage. The semiconductor device comprises an input circuit for inputting the external clock and outputting a reference signal, an output circuit for receiving an output timing signal and outputting an output signal according to the timing of the output timing signal, and an output timing control circuit for controlling the output timing so that the output signal exhibits a given phase relative to the external clock. The output timing control circuit includes a delay circuit for delaying the reference signal by a specified magnitude and generating an output timing signal, a phase comparison circuit for comparing the phase of the output timing signal with the phase of the reference signal, and a delay control circuit for specifying the magnitude of a delay to be produced by the delay circuit according to the result of comparison performed by the phase comparison circuit.

摘要翻译： 公开了一种用于输出具有相对于外部时钟保持的给定相位的输出信号的半导体器件，尽管特性差，温度变化和电源电压波动。 该半导体器件包括用于输入外部时钟并输出参考信号的输入电路，用于接收输出定时信号并根据输出定时信号的定时输出输出信号的输出电路和用于控制的输出定时控制电路 输出定时，使得输出信号相对于外部时钟呈现给定的相位。 输出定时控制电路包括用于将参考信号延迟指定幅度并产生输出定时信号的延迟电路，用于将输出定时信号的相位与参考信号的相位进行比较的相位比较电路和延迟控制 电路，用于根据由相位比较电路执行的比较结果来指定由延迟电路产生的延迟的大小。

公开(公告)号：US06829192B2

公开(公告)日：2004-12-07

申请号：US10335949

申请日：2003-01-03

申请人： Naoharu Shinozaki ,  Yasurou Matsuzaki

发明人： Naoharu Shinozaki ,  Yasurou Matsuzaki

IPC分类号： G11C700

CPC分类号： G11C11/40607 ,  G11C7/08 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40622 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4091 ,  G11C2207/2227 ,  G11C2211/4067 ,  G11C2211/4068

摘要： A partial area for retaining data during low power consumption mode is composed of a single first memory cell out of a plurality of memory cells connected to a bit line. An operation control circuit operates any of the memory cells selected in accordance with an address signal during normal operation mode for performing a read operation and a write operation. The operation control circuit keeps latching data retained by the first memory cell in the partial area into a sense amplifier during the low power consumption mode. This eliminates the need for a refresh operation for retaining the data in the first memory cell during the low power consumption mode. Since the data can be retained without a refresh operation, it is possible to reduce the power consumption during the low power consumption mode.

摘要翻译： 在低功耗模式期间用于保留数据的部分区域由连接到位线的多个存储单元中的单个第一存储单元组成。 操作控制电路在正常操作模式期间操作根据地址信号选择的任何存储单元，以执行读操作和写操作。 操作控制电路在低功耗模式期间将由部分区域中的第一存储单元保留的数据保持为读出放大器。 这消除了在低功耗模式期间需要用于将数据保持在第一存储单元中的刷新操作。 由于可以在不进行刷新操作的情况下保持数据，因此可以在低功耗模式下降低功耗。

公开(公告)号：US07295483B2

公开(公告)日：2007-11-13

申请号：US11513394

申请日：2006-08-31

申请人： Naoharu Shinozaki ,  Yasurou Matsuzaki

发明人： Naoharu Shinozaki ,  Yasurou Matsuzaki

IPC分类号： G11C7/00

CPC分类号： G11C11/40607 ,  G11C7/08 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40622 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4091 ,  G11C2207/2227 ,  G11C2211/4067 ,  G11C2211/4068

摘要： A partial area for retaining data during low power consumption mode is composed of a single first memory cell out of a plurality of memory cells connected to a bit line. An operation control circuit operates any of the memory cells selected in accordance with an address signal during normal operation mode for performing a read operation and a write operation. The operation control circuit keeps latching data retained by the first memory cell in the partial area into a sense amplifier during the low power consumption mode. This eliminates the need for a refresh operation for retaining the data in the first memory cell during the low power consumption mode. Since the data can be retained without a refresh operation, it is possible to reduce the power consumption during the low power consumption mode.

公开(公告)号：US20060291297A1

公开(公告)日：2006-12-28

申请号：US11513394

申请日：2006-08-31

申请人： Naoharu Shinozaki ,  Yasurou Matsuzaki

发明人： Naoharu Shinozaki ,  Yasurou Matsuzaki

IPC分类号： G11C7/10

CPC分类号： G11C11/40607 ,  G11C7/08 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40622 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4091 ,  G11C2207/2227 ,  G11C2211/4067 ,  G11C2211/4068

摘要： A partial area for retaining data during low power consumption mode is composed of a single first memory cell out of a plurality of memory cells connected to a bit line. An operation control circuit operates any of the memory cells selected in accordance with an address signal during normal operation mode for performing a read operation and a write operation. The operation control circuit keeps latching data retained by the first memory cell in the partial area into a sense amplifier during the low power consumption mode. This eliminates the need for a refresh operation for retaining the data in the first memory cell during the low power consumption mode. Since the data can be retained without a refresh operation, it is possible to reduce the power consumption during the low power consumption mode.

公开(公告)号：US20060007770A1

公开(公告)日：2006-01-12

申请号：US10968811

申请日：2004-10-20

申请人： Naoharu Shinozaki ,  Yasurou Matsuzaki

发明人： Naoharu Shinozaki ,  Yasurou Matsuzaki

IPC分类号： G11C7/00

CPC分类号： G11C11/40607 ,  G11C7/08 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40622 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4091 ,  G11C2207/2227 ,  G11C2211/4067 ,  G11C2211/4068

摘要： A partial area for retaining data during low power consumption mode is composed of a single first memory cell out of a plurality of memory cells connected to a bit line. An operation control circuit operates any of the memory cells selected in accordance with an address signal during normal operation mode for performing a read operation and a write operation. The operation control circuit keeps latching data retained by the first memory cell in the partial area into a sense amplifier during the low power consumption mode. This eliminates the need for a refresh operation for retaining the data in the first memory cell during the low power consumption mode. Since the data can be retained without a refresh operation, it is possible to reduce the power consumption during the low power consumption mode.

摘要翻译： 在低功耗模式期间用于保留数据的部分区域由连接到位线的多个存储单元中的单个第一存储单元组成。 操作控制电路在正常操作模式期间操作根据地址信号选择的任何存储单元，以执行读操作和写操作。 操作控制电路在低功耗模式期间将由部分区域中的第一存储单元保留的数据保持为读出放大器。 这消除了在低功耗模式期间需要用于将数据保持在第一存储单元中的刷新操作。 由于可以在不进行刷新操作的情况下保持数据，因此可以在低功耗模式下降低功耗。