Memory circuit with automatic refresh function
    2.
    发明授权
    Memory circuit with automatic refresh function 有权
    内存电路具有自动刷新功能

    公开(公告)号:US07345942B2

    公开(公告)日:2008-03-18

    申请号:US11413204

    申请日:2006-04-28

    申请人: Yasurou Matsuzaki

    发明人: Yasurou Matsuzaki

    IPC分类号: G11C7/00

    摘要: According to the present invention, a memory circuit requiring refresh operations a first circuit which receives a command in synchronization with a clock signal, and which generates a first internal command internally and a second circuit which generates a second internal command, e.g., a refresh command, internally in a prescribed refresh cycle. And an internal circuit, according to said first internal command, executes corresponding control through clock-synchronous operations, and when said refresh command is issued, sequentially executes control corresponding to the refresh command and control corresponding to said first internal command through clock-asynchronous operations. According to the present invention, when a refresh timing signal is generated, the refresh operation can be intrupted among the external command operations.

    摘要翻译: 根据本发明,一种需要刷新操作的存储电路,第一电路接收与时钟信号同步的命令,并且内部产生第一内部命令,第二电路产生第二内部命令,例如刷新命令 在规定的刷新周期内部。 并且根据所述第一内部命令,内部电路通过时钟同步操作执行相应的控制,并且当发出所述刷新命令时,通过时钟异步操作顺序执行对应于刷新命令的控制和对应于所述第一内部命令的控制 。 根据本发明,当产生刷新定时信号时,可以在外部命令操作中中断刷新操作。

    Memory circuit with automatic precharge function, and integrated circuit device with automatic internal command function
    3.
    发明申请
    Memory circuit with automatic precharge function, and integrated circuit device with automatic internal command function 审中-公开
    具有自动预充功能的记忆电路,具有自动内部指令功能的集成电路器件

    公开(公告)号:US20070206431A1

    公开(公告)日:2007-09-06

    申请号:US11790834

    申请日:2007-04-27

    申请人: Yasurou Matsuzaki

    发明人: Yasurou Matsuzaki

    IPC分类号: G11C11/4072

    摘要: According to the present invention, a memory circuit requiring refresh operations a first circuit which receives a command in synchronization with a clock signal, and which generates a first internal command internally and a second circuit which generates a second internal command, e.g., a refresh command, internally in a prescribed refresh cycle. And an internal circuit, according to said first internal command, executes corresponding control through clock-synchronous operations, and when said refresh command is issued, sequentially executes control corresponding to the refresh command and control corresponding to said first internal command through clock-asynchronous operations. According to the present invention, when a refresh timing signal is generated, the refresh operation can be interrupted among the external command operations.

    摘要翻译: 根据本发明,一种需要刷新操作的存储电路,第一电路接收与时钟信号同步的命令,并且内部产生第一内部命令,第二电路产生第二内部命令,例如刷新命令 在规定的刷新周期内部。 并且根据所述第一内部命令,内部电路通过时钟同步操作执行相应的控制,并且当发出所述刷新命令时,通过时钟异步操作顺序执行对应于刷新命令的控制和对应于所述第一内部命令的控制 。 根据本发明,当产生刷新定时信号时,可以在外部命令操作之间中断刷新操作。

    Semiconductor memory with single cell and twin cell refreshing
    4.
    发明授权
    Semiconductor memory with single cell and twin cell refreshing 有权
    半导体存储器与单细胞和双胞胎清爽

    公开(公告)号:US07154799B2

    公开(公告)日:2006-12-26

    申请号:US11098557

    申请日:2005-04-05

    申请人: Yasurou Matsuzaki

    发明人: Yasurou Matsuzaki

    IPC分类号: G11C7/00

    摘要: Flags are formed to respectively correspond to memory cell groups each including volatile memory cells. Each flag indicates as a set state that the memory cells store data in a second memory mode. In a changing operation of changing from a first memory mode in which data is independently retained by each memory cell to a second memory mode in which same data are retained in the memory cells of each memory cell group, each flag is reset in response to the first access to the corresponding memory cell group. Therefore, only the first access is made in the second memory mode in each memory cell group. The memory cells are accessed in a mode according to the flag in the changing operation, thereby allowing a system managing the semiconductor memory to freely access the memory cells even during the changing operation. Consequently, a practical changing time can be eliminated.

    摘要翻译: 标志分别形成为分别对应于包括易失性存储单元的存储单元组。 每个标志指示存储器单元将数据存储在第二存储器模式中的设置状态。 在从每个存储器单元独立地保持数据的第一存储器模式改变为在每个存储单元组的存储单元中保留相同数据的第二存储器模式的改变操作中,每个标志响应于 首先访问相应的存储单元组。 因此,在每个存储单元组中仅在第二存储器模式中进行第一次访问。 存储单元按照改变操作中的标志在模式下访问,从而即使在改变操作期间也允许管理半导体存储器的系统自由地访问存储单元。 因此,可以消除实际的改变时间。

    Semiconductor integrated circuit memory
    10.
    发明授权
    Semiconductor integrated circuit memory 有权
    半导体集成电路存储器

    公开(公告)号:US06185149B2

    公开(公告)日:2001-02-06

    申请号:US09340147

    申请日:1999-06-28

    IPC分类号: G11C800

    CPC分类号: G11C7/1018 G11C7/1072

    摘要: A semiconductor memory includes memory cell blocks, a burst-length information generating circuit which generates burst-length information based on a burst length, and a block enable circuit which receives the burst-length information. The block enable circuit selectively enables one of the memory cell blocks when the burst length is equal to or shorter than a predetermined burst length and selectively enables a plurality of memory cell blocks based on the burst length when the burst length is longer than the predetermined burst length. Data are read from the above-mentioned one or plurality of memory cell blocks.

    摘要翻译: 半导体存储器包括存储单元块,基于突发长度生成突发长度信息的突发长度信息产生电路,以及接收脉冲串长度信息的块使能电路。 当突发长度等于或小于预定突发长度时,块使能电路选择性地启用存储单元块中的一个,并且当突发长度长于预定突发时,基于脉冲串长度选择性地启用多个存储单元块 长度。 从上述一个或多个存储单元块读取数据。