A semiconductor packaging device comprises a carrier having at least a cavity/a slot thereon, at least a chip has a back surface and an active surface with a plurality of first bonding pads. The chip is affixed to the cavity to expose the active surface. A first insulating layer is on the active surface and the carrier comprises first plating through holes connected to first bonding pads and via the first insulating layer. A multi-layer structure on the first insulating layer comprises a plurality of conductive layout lines, second plating through holes therein, and a second insulating layer, exposed ball pads, and flip-chip pads thereon. The first plating through holes are electrically connected with the conductive layout lines, the second plating through holes, the exposed ball pads, and the flip-chip pads. The first solder balls are affixed to the ball pads.