发明申请
- 专利标题: Method for fabricating bit line of memory device
- 专利标题(中): 存储器件位线的制造方法
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申请号: US11490206申请日: 2006-07-19
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公开(公告)号: US20070020844A1公开(公告)日: 2007-01-25
- 发明人: Yi-Nan Chen , Tzu-Ching Tsai
- 申请人: Yi-Nan Chen , Tzu-Ching Tsai
- 申请人地址: TW TAOYUAN
- 专利权人: NANYA TECHNOLOGY CORPORATION
- 当前专利权人: NANYA TECHNOLOGY CORPORATION
- 当前专利权人地址: TW TAOYUAN
- 优先权: TWTW94124678 20050721
- 主分类号: H01L21/8242
- IPC分类号: H01L21/8242 ; H01L29/94
摘要:
A damascene process. A substrate covered by a dielectric layer and an overlying polysilicon masking layer with an opening exposing the underlying dielectric layer is provided. The exposed dielectric layer is etched to form a damascene opening therein and a portion of polysilicon masking layer remains on the dielectric layer. The remaining polysilicon masking layer is completely transformed into a metal polycide layer and then removed. A method for fabricating a bit line of a memory device is also disclosed.
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