Invention Application
US20070045836A1 Stacked chip package using warp preventing insulative material and manufacturing method thereof
审中-公开
使用防翘曲绝缘材料的堆叠芯片封装及其制造方法
- Patent Title: Stacked chip package using warp preventing insulative material and manufacturing method thereof
- Patent Title (中): 使用防翘曲绝缘材料的堆叠芯片封装及其制造方法
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Application No.: US11436822Application Date: 2006-05-18
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Publication No.: US20070045836A1Publication Date: 2007-03-01
- Inventor: Yong-Chai Kwon , Kang-Wook Lee , Keum-Hee Ma , Seong-Il Han , Dong-Ho Lee
- Applicant: Yong-Chai Kwon , Kang-Wook Lee , Keum-Hee Ma , Seong-Il Han , Dong-Ho Lee
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Priority: KR10-2005-0080655 20050831
- Main IPC: H01L23/48
- IPC: H01L23/48

Abstract:
In a stacked chip configuration, and manufacturing methods thereof, the gap between a lower chip and an upper chip is filled completely using a relatively simple process that eliminates voids between the lower and upper chips and the cracking and delamination problems associated with voids. The present invention is applicable to both chip-level bonding and wafer-level bonding approaches. A photosensitive polymer layer is applied to a first chip, or wafer, prior to stacking the chips or stacking the wafers. The photosensitive polymer layer is partially cured, so that the photosensitive polymer layer is made to be structurally stable, while retaining its adhesive properties. The second chip, or wafer, is stacked, aligned, and bonded to the first chip, or wafer, and the photosensitive polymer layer is then cured to fully bond the first and second chips, or wafers. In this manner, adhesion between chips/wafers is greatly improved, while providing complete fill of the gap. In addition, mechanical reliability is improved and CTE mismatch is reduced, alleviating the problems associated with warping, cracking and delamination, and leading to an improvement in device yield and device reliability.
Information query
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