A thin film transistor array substrate comprises thin film transistors and pixel electrodes formed at respective pixels that are defined by gate lines and data lines that orthogonally intersect each other. The thin film transistor array substrate further comprises a plurality of gate pad units that group a plurality of gate pads extended from the gate lines, and a plurality of data pad units that groups a plurality of data pads extended from the data lines. The thin film transistor array substrate further includes a plurality of gate test terminals connected to the gate pad units and beside at least one side of the respective gate pad units, and a plurality of data test terminals connected to the data pad units and located beside at least one side of the respective data pad units.