Invention Application
- Patent Title: RECESSED GATE TRANSISTOR STRUCTURE AND METHOD OF FORMING THE SAME
- Patent Title (中): 闭合闸门晶体管结构及其形成方法
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Application No.: US11560756Application Date: 2006-11-16
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Publication No.: US20070069268A1Publication Date: 2007-03-29
- Inventor: Min-Hee CHO , Ji-Young KIM
- Applicant: Min-Hee CHO , Ji-Young KIM
- Applicant Address: KR Gyeonggi-do
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR Gyeonggi-do
- Main IPC: H01L29/94
- IPC: H01L29/94 ; H01L27/108 ; H01L29/76 ; H01L31/119

Abstract:
Recessed gate transistor structures and methods for making the same prevent a short between a gate conductive layer formed on a non-active region and an active region by forming an insulation layer therebetween, even though a misalignment is generated in forming a gate. The method and structure reduce the capacitance between gates. The method includes forming a device isolation film for defining an active region and a non-active region, on a predetermined region of a semiconductor substrate. First and second insulation layers are formed on an entire face of the substrate. A recess is formed in a portion of the active region. A gate insulation layer is formed within the recess, and then a first gate conductive layer is formed within the recess. A second gate conductive layer is formed on the second insulation layer and the first gate conductive layer. Subsequently, source/drain regions are formed.
Public/Granted literature
- US07777258B2 Recessed gate transistor structure and method of forming the same Public/Granted day:2010-08-17
Information query
IPC分类: