Invention Application
- Patent Title: CHIP PACKAGE METHOD
- Patent Title (中): 芯片包装方法
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Application No.: US11613195Application Date: 2006-12-20
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Publication No.: US20070087480A1Publication Date: 2007-04-19
- Inventor: Su TAO , Kuang-Lin Lo , Tsung-Sheng Lee , Yaw-Yuh Yang , Yuan-Kai Tao
- Applicant: Su TAO , Kuang-Lin Lo , Tsung-Sheng Lee , Yaw-Yuh Yang , Yuan-Kai Tao
- Applicant Address: TW Kaohsiung
- Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
- Current Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
- Current Assignee Address: TW Kaohsiung
- Priority: TW91137974 20021231
- Main IPC: H01L21/78
- IPC: H01L21/78
Abstract:
The present invention relates to a method for manufacturing a semiconductor chip package structure including the following steps. A substrate is provided. A plurality of chips are assembled onto the substrate and are electrically connected with the substrate. A stiffener is assembled onto the substrate and the stiffener has a top surface and a bottom surface facing the substrate. A molding compound is formed to cover the semiconductor chip, the substrate, the top surface and the bottom surface of the stiffener. Afterwards, a singulation step is performed to cut the molding compound, the substrate and the stiffener.
Information query
IPC分类:
