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    Printed circuit boards and methods for fabricating the same
    1.
    发明申请
    Printed circuit boards and methods for fabricating the same 审中-公开
    印刷电路板及其制造方法

    公开(公告)号：US20050282314A1

    公开(公告)日：2005-12-22

    申请号：US11150346

    申请日：2005-06-13

    Applicant: Kuang-Lin Lo ,  Jen-Kuang Fang

    Inventor： Kuang-Lin Lo ,  Jen-Kuang Fang

    IPC: H01L21/44 ,  H05K3/24 ,  H05K3/40 ,  H05K3/42

    CPC classification number: H05K3/242 ,  H05K3/403 ,  H05K3/42 ,  H05K2201/0959 ,  H05K2201/09645 ,  H05K2203/1581 ,  H05K2203/175

    Abstract: Printed circuit boards and methods for fabricating the same. A via in a printed circuit board electrically connects to trace lines of the PCB, such that only one plating line is required to electrically connect a plating bus and the plating through hole. Thus, in an electroplating step, current can flow to fingers in the trace lines to plate an anti-oxidation metal layer thereon. The via is separated into several sub-vias to electrically isolate the plating line from trace lines and fingers, each of which connects to the plating line or the trace lines. Finally, at least one plating line remains, thus avoiding negative impact on electrical performance of an electronic device that uses the printed circuit board.

    Abstract translation: 印刷电路板及其制造方法。 印刷电路板中的通孔电连接到PCB的迹线，使得仅需要一条电镀线来电镀连接电镀母线和电镀通孔。 因此，在电镀步骤中，电流可以流到迹线中的指状物，以在其上镀上抗氧化金属层。 通孔被分成几个子通孔，以将电镀线与痕迹线和手指电隔离，每条线连接到电镀线或迹线。 最后，保留至少一个电镀线，从而避免对使用印刷电路板的电子设备的电气性能的负面影响。

    Packaging substrate with electrostatic discharge protection
    2.
    发明授权
    Packaging substrate with electrostatic discharge protection 有权
    包装基板采用静电放电保护

    公开(公告)号：US06777793B2

    公开(公告)日：2004-08-17

    申请号：US10289852

    申请日：2002-11-07

    Applicant: Meng-Tsang Lee ,  Kuang-Lin Lo

    Inventor： Meng-Tsang Lee ,  Kuang-Lin Lo

    IPC: H01L2302

    CPC classification number: H05K9/0067

    Abstract: The present invention relates to a packaging substrate with electrostatic discharge protection. The packaging substrate is deposited in a packaging mold, and the packaging mold comprises a plurality of injection pins for pushing the packaging substrate out of the packaging mold. A first copper-mesh layer and a second copper-mesh layer of the packaging substrate are electrically connected to each other via position pins. A bottom side of the packaging substrate comprises a plurality of recesses in positions corresponding to positions of the injection pins. The recesses pass the second copper-mesh layer to electrically connect the injection pins to the second copper-mesh layer, and static electric charges are conducted to the injection pins via the second copper-mesh layer and away from the packaging substrate. It prevents dies to be packaged from damage due to electrostatic discharge so as to raise the yield rate of semiconductor package products.

    Abstract translation: 本发明涉及具有静电放电保护的封装基板。 包装基材沉积在包装模具中，并且包装模具包括用于将包装基材推出包装模具的多个注射销。 封装基板的第一铜网层和第二铜网层通过位置引脚彼此电连接。 包装衬底的底侧包括与注射销的位置对应的位置的多个凹部。 凹槽通过第二铜网层以将注射针电连接到第二铜网层，并且静电荷通过第二铜网层并且远离封装衬底被引导到注射销。 它可以防止模具由于静电放电而受到损坏，从而提高半导体封装产品的成品率。

    Fabrication method for printed circuit board
    4.
    发明授权
    Fabrication method for printed circuit board 有权
    印刷电路板制造方法

    公开(公告)号：US07384566B2

    公开(公告)日：2008-06-10

    申请号：US11121091

    申请日：2005-05-04

    Applicant: Hung-Nan Chen ,  Jen-Kuang Fang ,  Kuang-Lin Lo

    Inventor： Hung-Nan Chen ,  Jen-Kuang Fang ,  Kuang-Lin Lo

    IPC: H01B13/00 ,  H05K3/02

    CPC classification number: H05K3/242 ,  H05K3/0035 ,  H05K3/06 ,  H05K3/28 ,  H05K2201/0989 ,  H05K2203/175 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49162

    Abstract: A fabrication method for PCBs. The method includes providing a substrate having a layout area and a periphery area around the layout area on a surface, forming a patterned wiring layer, having a bus line in the periphery area, a plurality of pads in the layout area, a plurality of bridge lines providing electrical connection between the pads, and a plating line electrically connecting the bus line and pads, overlying the substrate, forming a patterned solder mask over the substrate and wiring layer, the patterned solder mask having a plurality of first openings respectively exposing the pads and plating a metal layer respectively overlying the pads, forming a plurality of second openings respectively exposing the bridge lines between the pads, and removing the exposed bridge lines.

    Abstract translation: 一种PCB制造方法。 该方法包括提供具有在表面上的布局区域周围的布局区域和周边区域的基板，形成图案化的布线层，在周边区域中具有总线，布局区域中的多个焊盘，多个桥 在衬垫之间提供电连接的线，以及覆盖衬底的电连接总线和衬垫的电镀线，在衬底和布线层上形成图案化的焊料掩模，图案化的焊料掩模具有多个第一开口，分别暴露衬垫 以及分别覆盖覆盖在所述焊盘上的金属层，形成分别暴露所述焊盘之间的所述桥接线并且去除所暴露的桥接线的多个第二开口。

    Molding apparatus with a molding flowability sensor for packaging semiconductor device
    6.
    发明授权
    Molding apparatus with a molding flowability sensor for packaging semiconductor device 有权
    具有用于封装半导体器件的成型流动性传感器的成型装置

    公开(公告)号：US07144239B2

    公开(公告)日：2006-12-05

    申请号：US10901039

    申请日：2004-07-29

    Applicant: Wei-Chih Wang ,  Kuang-Lin Lo ,  Yun-Lung Chang

    Inventor： Wei-Chih Wang ,  Kuang-Lin Lo ,  Yun-Lung Chang

    IPC: B29C45/77

    CPC classification number: B29C45/7646 ,  B29C45/14639 ,  B29C2945/76056 ,  B29C2945/76063 ,  B29C2945/7626

    Abstract: A molding apparatus mainly comprises a mold chase holder, a mold chase, a heater and a molding flowability sensor. The mold chase comprises a mold cavity and a via, wherein the via penetrates a mold-cavity surface of the mold cavity. The mold chase is accommodated by a mold chase holder and there is a heater, for heating the mold chase up, disposed therein. And the molding flowability sensor for measuring the molding flowability of the instant molding flow at the mold-cavity surface of the mold cavity is provided at the mold-cavity surface of the mold cavity.

    Abstract translation: 成型装置主要包括模具支架，模具追踪器，加热器和成型流动性传感器。 模具追逐包括模腔和通孔，其中所述通孔穿过模腔的模腔表面。 模具追逐由模具夹持器容纳，并且设置有用于加热模具追加的加热器。 并且用于测量模腔的模腔表面处的即时成型流的成型流动性的成型流动性传感器设置在模腔的模腔表面。

    Fabrication method for printed circuit board
    7.
    发明申请
    Fabrication method for printed circuit board 有权
    印刷电路板制造方法

    公开(公告)号：US20050246892A1

    公开(公告)日：2005-11-10

    申请号：US11121091

    申请日：2005-05-04

    Applicant: Hung-Nan Chen ,  Jen-Kuang Fang ,  Kuang-Lin Lo

    Inventor： Hung-Nan Chen ,  Jen-Kuang Fang ,  Kuang-Lin Lo

    IPC: H01R43/00 ,  H05K3/00 ,  H05K3/06 ,  H05K3/24 ,  H05K3/28

    CPC classification number: H05K3/242 ,  H05K3/0035 ,  H05K3/06 ,  H05K3/28 ,  H05K2201/0989 ,  H05K2203/175 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49162

    Abstract: A fabrication method for PCBs. The method includes providing a substrate having a layout area and a periphery area around the layout area on a surface, forming a patterned wiring layer, having a bus line in the periphery area, a plurality of pads in the layout area, a plurality of bridge lines providing electrical connection between the pads, and a plating line electrically connecting the bus line and pads, overlying the substrate, forming a patterned solder mask over the substrate and wiring layer, the patterned solder mask having a plurality of first openings respectively exposing the pads and plating a metal layer respectively overlying the pads, forming a plurality of second openings respectively exposing the bridge lines between the pads, and removing the exposed bridge lines.

    Abstract translation: 一种PCB制造方法。 该方法包括提供具有在表面上的布局区域周围的布局区域和周边区域的基板，形成图案化布线层，在周边区域中具有总线，布局区域中的多个焊盘，多个桥 在衬垫之间提供电连接的线，以及覆盖衬底的电连接总线和衬垫的电镀线，在衬底和布线层上形成图案化的焊料掩模，图案化的焊料掩模具有多个第一开口，分别暴露衬垫 以及分别覆盖覆盖在所述焊盘上的金属层，形成分别暴露所述焊盘之间的所述桥接线并且去除所暴露的桥接线的多个第二开口。

    Multi-row substrate strip and method for manufacturing the same
    10.
    发明申请
    Multi-row substrate strip and method for manufacturing the same 有权
    多行基板条及其制造方法

    公开(公告)号：US20060091533A1

    公开(公告)日：2006-05-04

    申请号：US11258085

    申请日：2005-10-26

    Applicant: Yao-Ting Huang ,  Kuang-Lin Lo

    Inventor： Yao-Ting Huang ,  Kuang-Lin Lo

    IPC: H01L23/48 ,  H01L21/50

    CPC classification number: H01L23/49838 ,  H01L21/4846 ,  H01L21/565 ,  H01L23/5386 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A multi-row substrate strip mainly comprises a plurality of first and second substrate units in parallel, a plurality of connecting bars, a degating metal layer and at least one plating layer. The connecting bars are used to connect the first substrate units and connect the second substrate units. The degating metal layer comprises a plurality of runner portions on the connecting bars, a plurality of first gate portions and a plurality of second gate portions. The first gate portions are formed on the first substrate units, and the second gate portions are formed on the second substrate units. The plating layer is formed on the first gate portions and the second gate portions, and exposes the runner portions, so as to save the plating material.

    Abstract translation: 多列衬底条主要包括多个平行的第一和第二衬底单元，多个连接条，去金属层和至少一个镀层。 连接杆用于连接第一基板单元并连接第二基板单元。 脱金属层包括在连接杆上的多个流道部分，多个第一浇口部分和多个第二浇口部分。 第一栅极部分形成在第一基板单元上，并且第二栅极部分形成在第二基板单元上。 电镀层形成在第一栅极部分和第二栅极部分上，并露出流道部分，以便保存电镀材料。

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