A semiconductor memory device includes a memory cell including a floating body region in an electrically floating state and storing data by accumulating or discharging charges in or from the floating body region; a memory cell array including a plurality of the memory cells; a word line connected to a gate of the memory cell; a bit line connected to a diffusion layer of the memory cell; a sense amplifier connected to the bit line; and a decoder applying a first potential to the word line when data “1” is written to the memory cell and applying a second potential different from the first potential to the word line when data “0” is written to the memory cell.