公开(公告)号：US20120243294A1

公开(公告)日：2012-09-27

申请号：US13358677

申请日：2012-01-26

申请人： Mizuki Kaneko ,  Tomoki Higashi ,  Tomonori Kurosawa

发明人： Mizuki Kaneko ,  Tomoki Higashi ,  Tomonori Kurosawa

IPC分类号： G11C11/00

CPC分类号： G11C8/10 ,  G11C8/08 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0023 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2213/71 ,  G11C2213/72

摘要： According to one embodiment, a resistance-change memory includes bit lines, word lines, a memory cell array including memory cells arranged at intersections between the bit lines and the word lines, each of the memory cells including a variable-resistance element and a diode, a control circuit configured to apply a reverse bias to the diode, and to write data to a selected memory cell, and a current limiting circuit configured to limit a current flowing to the selected memory cell in a write. The current limiting circuit controls the current flowing to the selected memory cell not to exceed a second compliance current obtained by adding a leakage current from an unselected memory cell to a predetermined first compliance current.

摘要翻译： 根据一个实施例，电阻变化存储器包括位线，字线，包括布置在位线和字线之间的交叉处的存储单元的存储单元阵列，每个存储单元包括可变电阻元件和二极管 配置为向二极管施加反向偏置并将数据写入所选择的存储单元的控制电路，以及配置为限制在写入中流向所选存储单元的电流的限流电路。 电流限制电路控制流向所选存储单元的电流不超过通过将未选择的存储单元的泄漏电流加到预定的第一顺应电流而获得的第二顺从电流。

公开(公告)号：US07893478B2

公开(公告)日：2011-02-22

申请号：US12060522

申请日：2008-04-01

申请人： Tomoki Higashi ,  Takashi Ohsawa ,  Ryo Fukuda

发明人： Tomoki Higashi ,  Takashi Ohsawa ,  Ryo Fukuda

IPC分类号： H01L27/108 ,  H01L29/94 ,  H01L23/52 ,  H01L21/70 ,  H01L29/66

CPC分类号： H01L27/1022 ,  G11C11/4023 ,  G11C11/4026 ,  G11C11/405 ,  G11C11/4085 ,  G11C2211/4016 ,  H01L21/8249 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/1203 ,  H01L29/7841

摘要： This disclosure concerns a semiconductor storage device comprising a semiconductor layer provided on the insulation layer provided on the semiconductor substrate; a source layer and a drain layer provided in the semiconductor layer; a body provided between the source layer and the drain layer, the body being in an electrically floating state; an emitter layer contacting with the source layer, the emitter layer having an opposite conductive type to the source layer; a word line including the source layer, the drain layer, and the body, the word line being provided to memory cells arrayed in a first direction in a plurality of tow-dimensionally arranged memory cells; a source line connected to the source layers of the memory cells arrayed in the first direction; and a bit line connected to the drain layers of the memory cells arrayed in a second direction intersecting the first direction.

摘要翻译： 本公开涉及一种半导体存储装置，其包括设置在设置在半导体衬底上的绝缘层上的半导体层; 设置在所述半导体层中的源极层和漏极层; 设置在所述源极层和所述漏极层之间的主体，所述主体处于电浮动状态; 与源极层接触的发射极层，发射极层与源极层具有相反的导电类型; 包括源层，漏极层和主体的字线，字线被提供给在多个维度上排列的存储单元中沿第一方向排列的存储单元; 连接到沿着第一方向排列的存储单元的源层的源极线; 以及连接到沿与第一方向相交的第二方向排列的存储单元的漏极层的位线。

公开(公告)号：US20090180342A1

公开(公告)日：2009-07-16

申请号：US12352876

申请日：2009-01-13

申请人： Tomoki HIGASHI ,  Takashi Ohsawa

发明人： Tomoki HIGASHI ,  Takashi Ohsawa

IPC分类号： G11C7/06 ,  G11C7/00

CPC分类号： G11C11/404 ,  G11C11/406 ,  G11C2211/4016 ,  G11C2211/4065 ,  G11C2211/4068

摘要： A memory including; cells, wherein a refresh operation includes a first refresh and a second refresh, in the first refresh, a first potential higher than a gate potential in a retention is applied to the gate in a state having a source potential applied to the drain, and thereafter the gate potential in the retention is applied to the gate, thereby a first current passes to the cell, and in the second refresh, a second potential higher than a gate potential in the retention is applied to the gate, and a third potential higher than the gate potential in the retention is applied to the drain, thereby a second current passes to the cell, and a state of the cell is shifted to an equilibrium state in which amounts of the first and the second currents flowing during one cycle becomes substantially equal.

摘要翻译： 一个记忆包括 单元，其中刷新操作包括第一刷新和第二刷新，在具有施加到漏极的源极电位的状态下，将高于保持中的栅极电位的第一电位施加到栅极，之后 将保持中的栅极电位施加到栅极，由此第一电流流到电池，并且在第二次刷新中，将高于保持时的栅极电位的第二电位施加到栅极，并且第三电位高于 保留中的栅极电位被施加到漏极，由此第二电流流到电池，并且电池的状态转移到平衡状态，其中在一个周期期间流动的第一和第二电流的量变得基本相等 。

公开(公告)号：US07463541B2

公开(公告)日：2008-12-09

申请号：US12099647

申请日：2008-04-08

申请人： Tomoki Higashi ,  Takashi Ohsawa

发明人： Tomoki Higashi ,  Takashi Ohsawa

IPC分类号： G11C7/02

CPC分类号： G11C11/404 ,  G11C11/4099 ,  G11C2211/4016

摘要： A semiconductor storage device comprises information memory cells into which data can be written or from which data can be read; a memory cell array including the information memory cells arranged in a matrix; information word lines connected to the information memory cells in rows of the memory cell array; information bit lines connected to the information memory cells in columns of the memory cell array; a reference memory cell storing a single kind of digital data to generate a reference potential used to discriminate data stored in the information memory cells; a reference bit line connected to the reference memory cell; and sense amplifiers connected to the information bit lines and the reference bit line.

摘要翻译： 半导体存储装置包括信息存储单元，数据可以被写入其中，或从哪个数据可以被读取; 包括以矩阵排列的信息存储单元的存储单元阵列; 连接到存储单元阵列的行中的信息存储单元的信息字线; 连接到存储单元阵列的列中的信息存储单元的信息位线; 存储单一数字数据以产生用于区分存储在信息存储单元中的数据的参考电位的参考存储单元; 连接到参考存储单元的参考位线; 以及连接到信息位线和参考位线的读出放大器。

公开(公告)号：US20060023540A1

公开(公告)日：2006-02-02

申请号：US11049727

申请日：2005-02-04

申请人： Tomoki Higashi ,  Takashi Ohsawa

发明人： Tomoki Higashi ,  Takashi Ohsawa

IPC分类号： G11C7/02

CPC分类号： G11C11/404 ,  G11C11/4094 ,  G11C29/50 ,  G11C2211/4016

摘要： A semiconductor storage device comprises memory cells that store data by accumulating or releasing an electric charge; a memory cell array having a matrix arrangement of the memory cells; a plurality of word lines connected to memory cells aligned on rows of the memory cell array; a plurality of sub-bit lines connected to memory cells aligned on columns of the memory cell array; a bit line select circuit selecting the sub-bit line of a column; a main bit line connected to the sub-bit line selected by the bit line select circuit; a sense line detecting the potential of the sub-bit line selected by the bit line select circuit via the main bit line and reading data out of the memory cell; a write driver applying a voltage to the sub-bit line selected by the bit line select circuit via the main bit line and writing data into the memory cell; and a first switching element connected to the main bit line and turning on when the current flowing in the memory cell is detected externally via the sub-bit line without the use of the sense line or when a voltage is applied to the memory cell externally via the sub-bit line without the use of the write driver.

公开(公告)号：US20050195680A1

公开(公告)日：2005-09-08

申请号：US10864632

申请日：2004-06-10

申请人： Tomoki Higashi ,  Takashi Ohsawa

发明人： Tomoki Higashi ,  Takashi Ohsawa

IPC分类号： G11C11/406 ,  G11C8/00

CPC分类号： G11C8/08 ,  G11C11/4085

摘要： A semiconductor storage device comprises memory cells having a floating body region and storing data by accumulating or releasing electric charges in or from the floating body region; a memory cell array including a matrix arrangement of said memory cells; a plurality of word lines each connected to said memory cells of each row in the memory cell array; and a counter cell array including counter cells each provided in correspond to each said word line to store occurrences of activation of the word line to read out data from the memory cells.

摘要翻译： 半导体存储装置包括具有浮体区域的存储单元，并且通过在浮体区域中积聚或释放电荷来存储数据; 存储单元阵列，包括所述存储单元的矩阵排列; 多个字线，每个字线连接到存储单元阵列中的每一行的所述存储单元; 以及包括对应于每个所述字线的计数器单元的计数器单元阵列，以存储字线的激活以从存储器单元读出数据的发生。

公开(公告)号：US06310806B1

公开(公告)日：2001-10-30

申请号：US09716322

申请日：2000-11-21

申请人： Tomoki Higashi ,  Hiroaki Nakano

发明人： Tomoki Higashi ,  Hiroaki Nakano

IPC分类号： G11C700

CPC分类号： G11C29/84

摘要： A redundant memory circuit stores a defective row address. A switch circuit connects a spare row decoder with the wire for transmitting a row address signal according to the defective row address stored in the redundant memory circuit when the power supply is turned on. A row decoder deactivating circuit, when the power supply is turned on, deactivates the part of the row decoder corresponding to the defective row address according to the defective row address stored in the redundant memory circuit. As a result, when the row address buffer outputs the row address signal corresponding to the defective row address, the spare row decoder decodes the row address signal, thereby selecting a spare word line immediately.

摘要翻译： 冗余存储器电路存储有缺陷的行地址。 当电源接通时，开关电路根据存储在冗余存储器电路中的有缺陷的行地址，将备用行解码器与用于发送行地址信号的布线相连接。 行解码器去激活电路，当电源接通时，根据存储在冗余存储器电路中的有缺陷的行地址，去激活对应于有缺陷行地址的行解码器的部分。 结果，当行地址缓冲器输出与缺陷行地址对应的行地址信号时，备用行解码器解码行地址信号，从而立即选择备用字线。

公开(公告)号：US5825712A

公开(公告)日：1998-10-20

申请号：US912755

申请日：1997-08-18

申请人： Tomoki Higashi ,  Hiroyuki Noji

发明人： Tomoki Higashi ,  Hiroyuki Noji

IPC分类号： G11C11/401 ,  G01R31/28 ,  G11C29/00 ,  G11C29/02 ,  G11C29/50 ,  H01L21/66 ,  H01L21/822 ,  H01L27/04 ,  G11C7/00

CPC分类号： G11C29/025 ,  G11C29/02 ,  G11C29/50 ,  G11C29/50012 ,  G11C11/401

摘要： The present invention intends to provide a semiconductor device integrated circuit having an additive circuit capable of the evaluation of the dynamic performance of a memory block in a mixed logic and memory IC or a high-speed logic block in a semiconductor device integrated circuit, directly from the outside of the device. In order to evaluate the dynamic performance of the memory block or the high-speed logic block by using a tester, the device is provided on the chip with bus lines which bypass the peripheral logic and are connected to the input terminals of the memory block or the high-speed logic block. In the device, the delay time difference between the bus lines are measured from the outside of the device, at first. By use of the measurement result, the timing error of inputting a plurality of test pulse signals used for the dynamic performance evaluation is compensated. A switching element is provided between the reference line and each of the bus lines. A delay time measuring signal is input to each of external I/O pads connected to the bus line through which the delay time of the signal passing is measured, and then the differences in the delay time of all the bus lines are obtained on the basis of the signal delay time produced between the reference line and the each of the line. By use of the difference in the delay time of the lines, the input timing error when the memory block is measured with the tester is compensated, thereby precise evaluation of the memory block or the high-speed logic block is obtained.

摘要翻译： 本发明旨在提供一种半导体器件集成电路，其具有能够直接从半导体器件集成电路中的混合逻辑和存储器IC或高速逻辑块中的存储器块的动态性能评估的加法电路 设备的外部。 为了通过使用测试仪来评估存储器块或高速逻辑块的动态性能，该器件在芯片上提供有旁路外围逻辑并连接到存储器块的输入端的总线，或者 高速逻辑块。 在设备中，首先从设备的外部测量总线之间的延迟时间差。 通过使用测量结果，补偿了用于动态性能评估的输入多个测试脉冲信号的定时误差。 在参考线和每条总线之间提供开关元件。 延迟时间测量信号被输入到连接到总线的每个外部I / O焊盘，测量信号通过的延迟时间，然后基于所有总线的延迟时间的差异获得 在参考线和每条线之间产生的信号延迟时间。 通过使用线路的延迟时间的差异，补偿了使用测试器测量存储器块时的输入定时误差，从而获得存储块或高速逻辑块的精确评估。

公开(公告)号：US20080205181A1

公开(公告)日：2008-08-28

申请号：US12099647

申请日：2008-04-08

申请人： Tomoki Higashi ,  Takashi Ohsawa

发明人： Tomoki Higashi ,  Takashi Ohsawa

IPC分类号： G11C7/02

CPC分类号： G11C11/404 ,  G11C11/4099 ,  G11C2211/4016

摘要： A semiconductor storage device comprises information memory cells into which data can be written or from which data can be read; a memory cell array including the information memory cells arranged in a matrix; information word lines connected to the information memory cells in rows of the memory cell array; information bit lines connected to the information memory cells in columns of the memory cell array; a reference memory cell storing a single kind of digital data to generate a reference potential used to discriminate data stored in the information memory cells; a reference bit line connected to the reference memory cell; and sense amplifiers connected to the information bit lines and the reference bit line.

摘要翻译： 半导体存储装置包括信息存储单元，数据可写入到其中，或从哪个数据可以读取; 包括以矩阵排列的信息存储单元的存储单元阵列; 连接到存储单元阵列的行中的信息存储单元的信息字线; 连接到存储单元阵列的列中的信息存储单元的信息位线; 存储单一数字数据以产生用于区分存储在信息存储单元中的数据的参考电位的参考存储单元; 连接到参考存储单元的参考位线; 以及连接到信息位线和参考位线的读出放大器。

公开(公告)号：US07139216B2

公开(公告)日：2006-11-21

申请号：US10864632

申请日：2004-06-10

申请人： Tomoki Higashi ,  Takashi Ohsawa

发明人： Tomoki Higashi ,  Takashi Ohsawa

IPC分类号： G11C8/00 ,  G11C11/34

CPC分类号： G11C8/08 ,  G11C11/4085

摘要： A semiconductor storage device includes memory cells having a floating body region and storing data by accumulating or releasing electric charges in or from the floating body region; a memory cell array including a matrix arrangement of the memory cells; a plurality of word lines each connected to the memory cells of each row in the memory cell array; and a counter cell array including counter cells each provided in correspondence to each word line to store occurrences of activation of the word line to read out data from the memory cells.

摘要翻译： 半导体存储装置包括具有浮体区域的存储单元，并且通过在浮体区域中积聚或释放电荷来存储数据; 存储单元阵列，包括存储单元的矩阵排列; 多个字线，各自连接到存储单元阵列中的每一行的存储单元; 以及包括对应单元的计数单元阵列，每个单元对应于每个字线设置以存储字线的激活以从存储器单元读出数据的发生。