发明申请
- 专利标题: Pull-up circuit for an input buffer
- 专利标题(中): 用于输入缓冲器的上拉电路
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申请号: US11654445申请日: 2007-01-17
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公开(公告)号: US20070164804A1公开(公告)日: 2007-07-19
- 发明人: Pulkit Shah , Prasad Kotra
- 申请人: Pulkit Shah , Prasad Kotra
- 优先权: IN73/CHE/2006 20060117
- 主分类号: H03K5/08
- IPC分类号: H03K5/08
摘要:
An input buffer has a high voltage leg in parallel with a low voltage leg. The low voltage leg pulls up the pad when the pad voltage is below the power supply voltage. The high voltage leg remains off when the pad voltage is below the power supply. The low voltage leg is turned off when the pad voltage is above the power supply voltage. The high voltage leg is on when the pad voltage is above power supply voltage. A low voltage bias circuit and a high voltage bias circuit protect the transistors in the low and voltage legs when the pad voltage is above the power supply voltage. As a result, the pull-up circuit is high voltage tolerant and does not sink the current from pad.
公开/授权文献
- US07612585B2 Pull-up circuit for an input buffer 公开/授权日:2009-11-03
信息查询
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